Diamond chip, realized for the first time

Modern electronics is dominated by silicon complementary metal oxide semiconductor (CMOS) technology. However, silicon CMOS has always faced bottlenecks such as high power density, high frequency, high temperature, high radiation and other conditions.

Diamond is considered the ultimate semiconductor due to its superior properties compared to other semiconductors. Diamond CMOS devices have long strived to achieve performance beyond the capabilities of traditional silicon electronics. By using diamond electronics, not only are the thermal management needs of traditional semiconductors alleviated, but these devices are more energy efficient and can withstand higher breakdown voltages and harsh environments.

On the other hand, with the development of diamond growth technology, power electronics, spin electronics, and microelectromechanical systems (MEMS) sensors that can operate under high temperature and strong radiation conditions, the demand for peripheral circuits based on diamond CMOS devices has increased Improved monolithic integration. P-type diamond is easily obtained by bulk boron doping or surface transfer doping of hydrogen-terminated diamond surfaces. (P-type diamonds are readily accessible through bulk boron doping or surface transfer doping of a hydrogen-terminated diamond surface.) However, to achieve diamond CMOS, symmetric doping control must be achieved, just like what is achieved with the semiconductor silicon. Therefore, there is a need to develop diamond n-MOS.

However, n-channel diamond MOSFETs have long been an obstacle and have not yet been realized due to significant challenges in the growth of electronic-grade high-quality n-type diamond.

To date, phosphorus has been considered the only reliable shallowest n-type dopant at room temperature, despite the large covalent radius of P (1.08 Å) compared to C (0.77 Å) and High equilibrium formation energy (4–5.7 eV) ). However, due to the large carrier compensation in phosphorus-doped diamond, it is difficult to achieve n-type conductivity at a low donor concentration of about 1017cm-3, which hinders the development of n-channel MOSFETs. In addition to defects caused by the larger radius of phosphorus compared to carbon, the incorporation of large amounts of hydrogen into the diamond epitaxial layer during the chemical vapor deposition (CVD) process can also passivate phosphorus atoms and reduce conductivity.

In this study, electronic-scale n-type diamond with an atomically flat platform was realized based on the step-flow lateral growth mode. Therefore, N-type diamond with a low donor concentration of approximately 10 ¹⁷ cm ^-3 was obtained without observing hopping conductivity . Therefore, n-type diamond MOSFETs that can operate at 573 K have been successfully developed. The experimental field-effect electron mobility at 573 K is approximately 150cm ² V ^-1 s ^-1 , which is the highest among all wide-bandgap semiconductors at high temperatures.

We grew a phosphorus-doped diamond epitaxial layer on an Ib (111)-oriented high-pressure high-temperature (HPHT: high-pressure high-temperature) diamond substrate by microwave plasma chemical vapor deposition (MPCVD). n-type diamond contains two phosphorus-doped epitaxial layers: a lightly doped n-diamond epitaxial layer for the device channel and a heavily phosphorus-doped diamond epitaxial layer for the ohmic contact.

A 600 nm thick lightly doped n-layer diamond epitaxial layer was grown directly on the HPHT diamond substrate. Subsequently, a 100 nm thick heavy phosphorus-doped n+ layer was deposited on the n-layer using a homemade MPCVD reactor, which improved the efficiency of phosphorus doping into the diamond epitaxial layer. The grown diamond (111) has an unreconstructed monohydride-terminated surface. The homoepitaxial growth of n-type diamond on a diamond (111) substrate follows a step flow growth pattern.

Observed by atomic force microscopy (AFM), an atomically flat platform was formed (Figure 1A), as shown in Figure 1B; Figure S1 (Supporting Information), with an average roughness (Ra) ≈0.1 nm. Although steps are formed throughout the epitaxial layer, the average roughness of the terraces is ˂1 nm for a larger area of ​​10 × 10 µm (Figure S2, Supporting Information) ^. The terrace width is several hundred nanometers and the step height is approximately 3 nanometers (Figure S3, Supporting Information). Surface steps are caused by miscutting of the HPHT diamond (111) substrate.

由此可见，阶梯流生长模式产生了高质量的n-金刚石外延层。拉曼图（Raman mapping）显示金刚石的特征峰在0.135 cm ^-1 范围内表现出较小的色散，并且n-金刚石外延层的金刚石峰的半高全宽（FWHM：full-width at the half maximum）集中在1.75 cm ^-1 处，优于 HPHT 金刚石基材的1.95 cm ^-1 （图 1C、D）。

n-层中的应力低至-12 MPa ，晶体质量与在（100）金刚石基板上生长的同质外延金刚石层相当。如果假设压应力主要是由磷原子的掺入引起的，则 CVD 金刚石外延层中磷浓度的横向分布是均匀的。n + /n −的磷浓度 使用二次离子质谱 (SIMS：secondary ion mass spectrometry) 测量金刚石基底上的金刚石，如图 S4（支持信息）所示。100nm厚的n +层的磷浓度为约10 ²⁰ cm ^-3 。600nm厚的轻掺杂n -层金刚石外延层的磷浓度为N D ≈10 ¹⁷ cm ^-3 。SIMS 数据中可以观察到磷浓度沿生长方向均匀分布。

另外，SIMS深度剖面显示氢含量被控制在10 ¹⁷ cm ^-3 的噪声水平。磷和氢原子良好控制地掺入金刚石外延层意味着金刚石外延层具有高晶体质量，这对于实现 n 型导电性至关重要。此外，没有从外延层检测到与氮空位（nitrogen-vacancy）相关的发光。

图1

由于金刚石中磷的深层性质，电子浓度很大程度上取决于温度。电子浓度计算如下：

其中n表示导带中的自由电子浓度，N _D 表示磷浓度（phosphorous concentration），N _A 表示补偿受主密度（compensating acceptor density），N _C 表示有效导带态密度（effective conduction band density of states），g表示施主简并因子（degeneration factor of the donors），E _D 表示供体的活化能（the activation energy of the donors），k _B 是玻尔兹曼常数，T表示温度。

电子密度在 300 K 时约为 10 ¹⁰ cm ^-3 ，在 573 K 时增加了四个数量级，N _D 约为10 ¹⁷ cm ^-3 （图 S5，支持信息）。补偿受主浓度N _A 约为2×10 ¹⁶ cm ^-3 。在室温下，通过霍尔效应测得的电子迁移率约为623cm ² V ^-1 s ^-1 。轻掺杂的n -层即使在573 K 时也表现出212cm ² V ^-1 s ^-1 的高电子迁移率（图S6，支持信息）。轻掺杂n -层薄膜的电阻率在室温下约为10 ⁶ Ω cm，在573 K时降至100Ω cm（图 S7，支持信息），热活化能E _D 约为0.57 eV。

我们制造了具有两种几何形状的 n 沟道金刚石 MOSFET：rectangular 和Corbino（图 2；表 S1，支持信息）。源极（S）和漏极（D）接触形成在重磷掺杂的n+层上，该层是退火（annealed）的Ti（50 nm）/Pt（10 nm）/Au（60 nm）。重掺杂 n +金刚石的电阻率在室温下约为 80 Ω cm，在 573 K 时为 20 Ω cm。轻掺杂磷 n -层用作 MOSFET 的沟道。S 和 D 电极之间的顶部重掺杂 n +金刚石层在氧等离子体中蚀刻，直到到达轻掺杂层。

栅极氧化物是在 473 K 下通过原子层沉积 (ALD) 沉积的 30 nm 厚的 Al ₂ O ₃ 。栅极金属由 10 nm 厚的 Ti 层和 60 nm 厚的 Au 层覆盖组成。栅极长度( L _g )为5μm和10μm，源极-漏极( L _sg )和漏极-栅极间隔( L _dg )分别为5μm和10μm。

Corbino MOSFET 栅极的内径和外径分别为 220 µm 和 230 µm。对于此处研究的rectangular MOSFET（1 号器件），L _g 为 5 µm，L _sg = L _dg = 10 µm，栅极宽度约为 900 µm。图 2A、B分别显示了 n 型金刚石 MOSFET 的原理图和光学图像。MOSFET 的电气特性是在真空室 (10 ^-3 Pa) 中使用半导体参数分析仪和屏蔽探针台进行的。为了进行电气特性表征，MOSFET 的温度从室温升至 573 K。

图2

图2C显示了矩形 MOSFET 的 漏极电流 ( I _d )（通过栅极宽度归一化）与漏极电压 ( V ds )的关系。在这里，我们展示了在三个温度下测量的I _d – V _ds 特性：300 K (RT)、423 K (150 °C) 和 573 K (300 °C)。MOSFET 的栅极电压 ( V _gs ) 在 -20 至 10 V 之间变化，步长（steps）为 5 V。漏极电流由栅极电压很好地调制，显示出典型的 n 型沟道晶体管行为。V _ds = 20 和V _gs = 5 V 时的最大漏极电流 ( I _d,sat )在 300 K 时约为 0.027 µA mm ^-1 。然而，进一步增加V _gs > 5 V 导致漏极电流几乎没有改善，因为到高串联电阻。直到 MOSFET 的漏极电流在某个温度下随时间稳定为止，获得与温度相关的I _d − V _ds 特性。

如图2C(ii)、(iii)所示 ，由于磷的热电离，漏极电流随着温度的升高而显着增加。在高温下且V _ds = 20 V 和V _gs = 10 V 时，漏极电流在 423 K 时增加至 2.9 µA mm ^-1 ，在 573 K 时增加至 10 ⁵ µA mm ^-1 ，分别比该值高出两个和四个数量级分别为 300 K。这与电阻率对温度的依赖性一致（图 S7，支持信息）。达到饱和所需的漏极电压随着温度和栅极电压的增加而增加，即在 573 K 和V _gs = 10 V时饱和时，V _ds > 30 V。估计导通电阻在 RT 时约为 5 GΩ mm ，在 573 K、 V _gs = 10 V时减小至 160 kΩ mm。其他温度下 MOSFET 电气特性的变化如图 S8 – S12（支持信息）所示。不同栅极电压下漏极电流对测量温度的依赖性（图 S13，支持信息）。漏极电流随温度呈指数增加。使用温度相关漏极电流的阿伦尼乌斯方程进行拟合可提供 0.45 eV 的热活化能。

MOSFET 的传输特性或与栅极电压相关的漏极电流如图3A （ 300 K 时）和图 3C（573 K（573 K）、 饱和区V _ds = 20 V 时）。在V _ds = 20 V 时，栅极电压为 10 V 和 −20 V 时的漏极电流比在 RT 下 > 200，在 573 K 下为 100 倍 。与基于硼掺杂金刚石的 MOSFET 类似，n 型金刚石 MOSFET 表现出深度耗尽模式。在低于 473 K 的温度下，在传输曲线中观察到很小的滞后。在 573 K 时仅观察到轻微的滞后。最大跨导g _m 在 300 K 时约为 0.012 µS mm ^-1 ，在 573 K 时约为 4 µS mm ^-1 。使用V _gs 与I _d ^0.5 的图形方法提取阈值电压 ( V th ) （图 3B，D ），即 ≈−25 V。V th随栅极扫描方向、栅极扫描方向或温度的变化很小（图4A）。还测量了具有不同几何形状的其他器件，其电气特性如图S14 – S17 （支持信息）所示，并且观察到了类似的 n 沟道行为。例如最大饱和漏极电流、最大跨导、阈值电压和温度等电气性能，与具有相似尺寸的 MOSFET 相当（表 S1，支持信息）。

图3

图4

对于迁移率不依赖于栅极电压或串联电阻的理想 MOSFET，可以使用饱和区的二次模型计算有效电子迁移率 µ _eff ，如下所示：

其中 I _d,stat 表示饱和区的漏极电流，C _ox 表示栅极氧化物的电容。我们尝试使用方程（ 2 ）确定场效应电子迁移率。然而，在300 K时，场效应迁移率低至0.02cm ² V ^-1 s ^-1 ，明显偏离霍尔测量所测得的合理值（低近3000倍）。将串联电阻代入等式（2）不会导致迁移率发生本质变化。随着温度的升高，观察到场效应电子迁移率增加，这是不合理的。在573 K时，使用公式（ 2 ）计算出的电子迁移率约为150 cm ² V ^-1 s ^-1 （图 4B），在高温下远高于基于SiC、GaN和Ga ₂ O ₃ 的n沟道MOSFET 。请注意，由于源极/漏极和漂移区中的大串联电阻以及金刚石中磷的部分热电离，即使在 573 K 时迁移率也被低估。

为了精确评估场效应迁移率，我们考虑 i) 磷供体的热电离效率，ii) 串联电阻，以及 iii) 迁移率降低因素（即缺陷散射）。因此，在线性区，漏极电流（I d）可表示为：

其中M表示施主占据因子（donor occupancy factor），即束缚施主电荷与通道电荷的比率（a ratio of bound donor charge to channel charge），反映施主的电离率（ionization rate of the donor ），并与电子的准费米能级（the quasi Femi level of electrons）相关。

在这里，我们假设 M 与沟道深度无关。请注意，M 的解析形式与自由电子密度与掺杂密度之比不同（支持信息）。M越大，自由电子密度与掺杂密度的比值越小。α 是与施主浓度相关的降低漏极电流的因子，此处约为 1.1。γ 包括调节迁移率的 θ 和 η 因子（支持信息）。因子θ与常规载流子散射和串联电阻的影响有关。漏极电压对载流子迁移率的影响与γ中包含的参数η有关。非零的 η 主要是由于氧蚀刻导致纳米级/微米级台面结构的不规则性。在远高于阈值电压的区域中模拟电子迁移率。由于漏极电压小、源漏极距离大、栅极长度大，不考虑载流子速度的饱和。

模拟中金刚石中磷的热电离设定为 0.57 eV。我们获得了n型MOSFET在0V栅极电压下的场效应迁移率，如图 4C所示。在300 K 时迁移率模拟为约638 cm ² V ^-1 s ^-1 ，考虑施主占据因子M 和串联电阻，迁移率在573 K 时降低至约200 cm ² V ^-1 s ^-1 。对于理想的 MOSFET，M 随着电流的增加而减小，最终达到零。M 在 300 K 时计算为 2278，在 573 K 时降至 ≈4（图 S18，支持信息），揭示了 n 型金刚石 MOSFET 耗尽模式。值得注意的是，没有考虑补偿受体效应。通过考虑施主占用因子和串联电阻，漏极电压与漏极电流的模拟特性显示在 SM 中（图 S19 ，支持信息）。低漏极电压区域存在轻微差异，主要是由于S 和 D 电极中n +和 n -层之间的势垒所致。

We note that the simulations were performed assuming that the entire n-layer is conductive. Considering the Femi level pining of oxygen-terminated phosphorous-doped n-type (111) diamond, subsurface depletion of the channel will occur. Simulations using a similar n-metal Schottky FET - channel diamond layer showed a sub-depletion layer of about 50 nm. For n-type MOSFETs, pining along the Femi level of a fixed charge in the insulator modifies the Femi potential in the simulation. Detailed experimental and theoretical studies should be performed to reveal the impact of future defect states.

At present, p-channel diamond MOSFETs have been widely developed and conventional manufacturing processes have been established. Due to the lack of diamond n-MOS, it has been reported that complementary circuits can be realized using diamond p-MOS and III-nitride n-MOS. While this is a promising strategy, all-diamond CMOS is the ultimate pursuit to fully exploit the diamond figure of merit, especially for electronics operating in harsh environments (high temperatures and strong radiation). For high-frequency operation, compared with H-side transistors with cutoff frequencies exceeding GHz, the series resistance of n-type diamond MOSFETs is still large, exceeding 10 ⁹ Ω mm ^-1 at room temperature . Therefore, the operating speed is limited to the kilohertz range. However, at temperatures >573 K, the series resistance decreases by more than three orders of magnitude. The switching speed is ˂ 5 µs (Figure 4D) and can also be adjusted by the signal applied to the gate.

The larger the gate amplitude, the faster the switching speed due to the increase in channel conductivity. By optimizing the device geometry, such as reducing the drift region space and gate length, the operating frequency can exceed the megahertz range and easily meet the requirements of mixed-signal circuits for radiation detectors and MEMS sensors. In addition, n-type diamond can stabilize the negatively charged nitrogen vacancy (NV-) state, greatly improving sensitivity. Therefore, diamond CMOS integrated NV centers facilitate the development of diamond spintronic devices that require specialized controllability and integrity to extend quantum sensing protocols.

The deep nature of phosphorus in diamond favors surface p-type conductivity in lightly doped phosphorus diamond epitaxial layers with hydrogen termination. Therefore, diamond CMOS based on lightly doped n-type diamond planar technology can be realized. By using MEMS technology to design the band structure, the performance of n-type diamond MOSFETs can be further improved. This research reveals monolithically integrated diamond chips in which electronics, spintronics and sensors are all based on diamond.

In summary, an n-channel diamond MOSFET was demonstrated on a phosphorus-doped homoepitaxial (111) diamond epitaxial layer. The n-type (111) diamond epitaxial layer is grown based on the step-flow nucleation mode, which can precisely control the crystal quality and donor distribution. n-MOSFET exhibits a high mobility of approximately 150 cm ² V ^-1 s ^-1 at 573 K, which is a remarkable feature superior to other wide-bandgap semiconductors at high temperatures. The excellent high-temperature performance provides avenues for the development of diamond CMOS circuits for high-power electronics in harsh environments, integrated spintronics, and extreme sensors.

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