Small chip interconnection takes a crucial step! UCIe IP successfully achieves cross-vendor interoperability

Latest update time：2024-03-25

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Artificial intelligence, high-performance computing, ultra-large-scale data centers and other fields have put forward increasingly higher requirements for chip performance and functions. Traditional chip design and manufacturing models have been unable to meet these needs. Chiplets and heterogeneously integrated Multi-Die systems bring new hope for solving these problems.

By heterogeneously integrating multiple chips in a single package, Multi-Die systems can provide greater processing power and performance. A series of technological innovations paved the way for the emergence of Multi-Die systems, one of the key ones being the UCIe standard. Launched in March 2022, UCIe is the de facto standard for die-to-die connectivity and is intended to build a broader ecosystem around proven chips, or chiplets.

UCIe was founded to simplify interoperability between chips from different vendors and different process technologies. So, can the UCIe standard be implemented? The answer is yes. Synopsys and Intel have successfully used the UCIe standard to achieve interoperability between different processes and IP from different manufacturers.

Synopsys and Intel achieve major breakthrough in UCIe interoperability testing

In late summer 2023, at the Intel On technology innovation conference, Synopsys and Intel joined hands to achieve a milestone achievement: in the Universal Core Interconnect (UCIe) interoperability test chip demonstration, both parties based on their respective UCIe PHY IP successfully enables robust UCIe traffic transmission.

This successful UCIe test chip demonstration is a new result of the long-term cooperation between Synopsys and Intel. To demonstrate the interoperability of the chips at work, Intel turned to Synopsys, the first company in the industry to provide usable UCIe IP. During this period, multiple teams from all over the world participated in the test. In addition to packaging design, the team also performed extensive pre-tape work, such as using Synopsys VCS® functional verification solution to simulate each test chip to identify possible problems.

Intel's test chip, Pike Creek, consists of Intel UCIe IP chiplets built on Intel 3 technology. It is combined with Synopsys UCIe IP test chips manufactured using TSMC's N3 process. This successful combination mimics the mixing and matching of chips that would occur in a real-life Multi-Die system, proving that this approach is commercially viable.

This collaboration between Synopsys and Intel is of great significance as they provide valuable experience for the promotion and application of the UCIe standard. Currently, both parties plan to share some of the lessons learned with the UCIe Alliance. The UCIe Alliance oversees the UCIe standard and is developing a compliance plan for the standard.

Some lessons learned include:

Utilize existing test chips for evaluation: Since chip manufacturing takes a long time, and verifying that everything is working as expected requires a lot of cost and time, it is important for both parties to find a way to use existing test chips to evaluate compatibility Ideal.

Pay attention to the overall planning of Multi-Die systems: Designing Multi-Die systems requires comprehensive planning, especially when reusing packages or circuit board designs is required. Providing as much flexibility as possible on the board provides more options for later use.

The importance of open standards: Open standards like UCIe provide guarantees for device interoperability. When both ends of the link are controlled by the same company, there is no need to worry about whether the two ends are compatible. But in the next few years, there may be many companies that are unwilling to do both, and will instead choose to buy components from the market.

There is a basis for IP mash-up: chiplets help reduce manufacturing costs at advanced process nodes and enable designs to be partitioned to include multiple process nodes. Without corresponding standards, IP availability will be limited, and selecting process nodes based on IP availability is naturally not the best approach. The UCIe test chip interoperability demonstration provides a tangible basis for mixing and matching IP designs and lays the foundation for an open chiplet ecosystem.

UCIe IP: Opening the Door to Multi-Die System Reliability and Performance

One of the advantages of the Multi-Die system architecture is that it can be composed of chips from different suppliers and based on different process nodes. This provides flexibility in controlling costs and even optimizing power, performance and area (PPA). UCIe is a key element in bringing different components together and enabling them to communicate with each other, while supporting a range of advanced packaging technologies. The UCIe Alliance sees UCIe as a major enabler of an open chiplet ecosystem. Such an ecosystem could trigger a new wave of custom chip innovation to satisfy the insatiable thirst for performance in today’s ubiquitous AI, connectivity and cloud computing.

However, even if a UCIe-compliant Multi-Die system performs well during development, testing, and manufacturing, developers still need to ensure that the die-to-die connection in the actual system remains reliable at all times. This is required not only during the development and manufacturing stages, but also after the design has been running for many years. This is where UCIe IP plays an important role.

Due to the complexity of Multi-Die systems, improving the quality level in the SoC is critical. Achieving this correctly requires the use of high-quality building blocks (chips and IP), simulation and verification tools, and ongoing testing and field monitoring (including remediation) to be able to proactively resolve any issues.

UCIe IP generally consists of the following three parts: a controller to achieve low latency between chips based on common protocols such as PCIe, CXS and streaming protocols; a PHY to enable high-performance and low-power connectivity in the package; Verification IP, used to speed up verification convergence. Built-in testability capabilities enable developers to identify defective dies during the die test phase.

The benefits of choosing UCIe standard IP for Multi-Die systems are mainly reflected in:

Choosing UCIe-compliant interface IP enables seamless connectivity and interoperability between chips without impacting the entire system.

Additionally, in addition to testability features for known-good chips, IP can provide cyclic redundancy check (CRC) or parity checking for error detection, and retry functionality for error correction.

All in all, UCIe IP is critical to ensuring the reliability and performance of Multi-Die systems. Choosing the right UCIe IP can help developers reduce risk, speed time to market, and improve the quality of the final product.

Summarize

As Multi-Die systems become more widely used, they are expected to become mainstream technology in the next few years. Faced with highly interdependent and complex designs such as Multi-Die, chip developers need the close collaboration of the entire semiconductor ecosystem to maximize their potential. The success of this test by Intel and Synopsys marks a key step for UCIe technology and lays a solid foundation for the future development of Multi-Die system chip interconnect technology. Intel plans to continue working with Synopsys to further develop UCIe solutions.

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