High NA EUV lithography machine price revealed, everything is ready for mass production

芯片制造商依靠微缩——制造更小的晶体管并将更多的晶体管封装到硅晶圆上——来推动微芯片技术的进步。这并不是改进芯片的唯一方法；例如，新颖的架构也可以提高性能。但 摩尔定律 本质上成为普遍法则是有原因的 ：50 多年来，“收缩”一直是计算能力指数级增长的幕后推手。

多年来，我们一直在将深紫外 (DUV) 光刻技推向极限。为了减小可打印的最小特征的尺寸（称为临界尺寸 (CD)），我们可以转动两个主要旋钮：光的波长 λ 和 数值孔径 NA。然而，现在我们的 DUV 系统中已经没有多少空间可以调整这些旋钮了。

EUV 光刻使我们能够对波长旋钮进行重大调整：它使用 13.5 nm 光，而最高分辨率 DUV 系统则使用 193 nm 光。当我们的第一个预生产 EUV 光刻平台 NXE 于 2010 年首次发货时，它的 CD 从 DUV 的 30 nm 以上下降到 EUV 的 13 nm。

高数值孔径（High NA） EUV 是我们不断追求微缩的下一步。与 NXE 系统一样，它使用 EUV 光在硅晶圆上打印微小特征。通过调整 NA ，我们可以提供更好的分辨率：名为 EXE 的新平台为芯片制造商提供 8 纳米的 CD。这意味着他们可以打印比 NXE 系统小 1.7 倍的晶体管，从而实现晶体管密度高 2.9 倍。

我们如何在高数值孔径 EUV 系统中获得更高的分辨率？芯片制造商为何投资新技术？这对你来说意味着什么？请继续阅读以下文章以了解更多信息。

高数值孔径 EUV 光刻技术的主要进步是新的光学器件。名称中的“NA”指的是数值孔径——衡量光学系统收集和聚焦光线的能力。它被称为High NA EUV，因为我们将 NA 从 NXE 系统中的 0.33 增加到 EXE 系统中的 0.55。NA 越高，系统的分辨率就越高。

蔡司的高数值孔径 EUV 反射镜测试

（图片来源：ZEISS SMT）

实现数值孔径的增加意味着使用更大的镜子。但更大的镜子会增加光线照射到刻线的角度，刻线上有要打印的图案。在较大的角度下，掩模版会失去反射率，因此图案无法转移到晶圆上。这个问题本来可以通过将图案缩小 8 倍而不是 NXE 系统中使用的 4 倍来解决，但这需要芯片制造商改用更大的掩模版。

相反，EXE 采用了巧妙的设计：变形光学。该系统的镜子不是均匀地缩小正在打印的图案，而是在一个方向上将其缩小 4 倍，在另一个方向上缩小 8 倍。该解决方案减少了光线照射十字线的角度并避免了反射问题。重要的是，它还允许芯片制造商继续使用传统尺寸的掩模版，从而最大限度地减少了新技术对半导体生态系统的影响。

由于采用变形光学器件，EXE 系统的曝光场大小是其 NXE 前身的一半。因此，对单个晶圆进行图案化需要两倍的曝光次数。

开放式、完全组装的 TWINSCAN EXE:5000

两倍的曝光次数可能意味着打印晶圆的时间延长一倍。相反，我们将其视为一个挑战。解决方案？更快的晶圆和掩模版台。EXE 系统中的晶圆台加速至 8g，是 NXE 晶圆台速度的两倍。EXE 的十字线阶段的加速速度（reticle stage accelerates）是 NXE 的四倍 – 32g，相当于一辆赛车在 0.09 秒内从 0 加速到 100 公里/小时。

凭借其新平台，TWINSCAN EXE:5000 每小时可打印超过 185 个晶圆，与已在大批量制造中使用的 NXE 系统相比有所增加。我们制定了到 2025 年将产能提高到每小时 220 片晶圆的路线图。这种生产力对于确保将高数值孔径集成到芯片工厂对于芯片制造商来说在经济上可行至关重要。

高数值孔径 EUV 光刻将使芯片制造商能够在最先进的微芯片上打印最小的特征。但与此同时，芯片制造商并没有只是袖手旁观。他们找到了其他方法，通过使用更复杂的生产工艺来解决光刻系统的分辨率限制。

这些解决方法是有代价的。它们增加了生产时间，并提供了额外的机会引入可能影响芯片性能的缺陷。EXE:5000 的 CD 为 8 纳米，使芯片制造商能够简化其制造流程。结果？更经济高效地生产先进微芯片。

EXE:5000 代表了 EUV 光刻技术的发展，而不是一场革命。我们尽可能多地重用了现有的 EUV 技术，并且仅更改了提供系统分辨率和生产力增强所必需的方面。而且，与我们的 NXE EUV 系统一样，EXE 系统由可以在集成到完整系统之前进行独立测试的模块组成。

为什么我们在整个 EUV 光刻系统中优先考虑通用性和模块化？因为这样我们的所有系统都会受益于 20 多年 EUV 开发的经验教训。使用经过尝试和测试的技术可以降低出现问题的风险。这些模块简化了系统的安装和集成到客户晶圆厂的过程。这意味着系统将更快地开始生产芯片——我们的客户将在 2024 年至 2025 年开始研发，并在 2025 年至 2026 年进入大批量生产。

快速的时间表对每个人来说都是个好消息：这些系统越早开始打印最先进的芯片，它们所支持的尖端技术就越早可用。

组装 TWINSCAN EXE:5000

EXE:5000 的 8 nm 分辨率意味着芯片制造商可以将更多晶体管封装到单个芯片中。更小的晶体管更加节能——这意味着芯片将能够用更少的资源做更多的事情。因此，EXE:5000 打印的微小特征将构成最先进微芯片的基础。而且，由于系统的生产力，芯片制造商可以大量制造这些芯片。

芯片创新在当今的数字世界中变得越来越重要。消费者期望新型和新一代的电子设备体积更小、功能更多、更好、更快。借助高数值孔径 EUV 光刻技术，芯片制造商可以满足这些消费者的需求。

第一批使用 EXE:5000 制造的芯片将是 2 nm 节点逻辑芯片。类似晶体管密度的存储芯片也将随之而来。这些芯片将把最微小的功能与领先的架构相结合，为未来的技术提供动力：机器人、人工智能、物联网等等。

"Hyper-NA with an NA above 0.7 is certainly an opportunity that will become more apparent starting around 2030," ASML chief technology officer Martin van den Brink wrote in ASML's 2023 annual report. "It Probably most relevant to Logic and needs to be more affordable than "high NA EUV " dual patterning, but it could also be an opportunity for DRAM and the key for us is that Hyper-NA is driving our overall EUV capability platform to that. Improve costs and delivery times."

ASML's current EUV tools include a low NA model with 0.33 NA optics enabling a critical dimension (CD ) of 13.5 nm . This is sufficient to produce a minimum metal spacing of 26 nm and an approximate interconnect space spacing of 25-30 nm tip-to-tip from a single exposure pattern. These sizes are sufficient to meet the needs of 4nm/5nm level production nodes. Still, the industry still needs 21-24nm pitches at 3nm, which is why TSMC’s N3B process technology is designed to print the smallest possible pitches using Low-NA EUV dual pattern printing. This method is considered very expensive.

Next-generation High NA EUV systems with 0.55 NA optics will enable CD at 8nm, which is enough to print minimum metal pitches of about 16nm, which will be useful for nodes beyond 3nm, and is expected to be even for 1nm, at least according to Imec 's vision so.

But metal pitches will become smaller, exceeding 1nm, so the industry will need more sophisticated tools than ASML's High-NA devices. This allowed us to develop Hyper-NA tools with higher numerical aperture projection optics. ASML Chief Technology Officer Martin van den Brink confirmed in an interview that the feasibility of Hyper-NA technology is being studied. However, no final decision has been made yet.

Increasing the numerical aperture of projection optics is a costly process that involves significant changes in the design of lithography tools. In particular, this includes the physical size of the machine, the need to develop many new components and the impact of increased costs. ASML recently revealed that low numerical aperture EUV Twinscan NXE machines will cost $183 million or more, depending on configuration, while high numerical aperture EUV Twinscan EXE tools will cost $380 million or more, depending on configuration. Hyper-NA will cost more, so ASML will have to answer two questions: whether it's technically achievable and whether it's economically viable for leading logic chip makers. Only three leading chipmakers remain: Intel, Samsung Foundry and TSMC. Japan's Rapidus has yet to develop into a viable competitor. So while Hyper-NA EUV lithography is needed, it must be affordable.

“The introduction of Hyper-NA will depend on how much we can reduce costs,” Martin van den Brink told Tweakers.net last year. “I have traveled the world many times and discussed with customers the need and desirability of Hyper-NA. In recent months I have gained the confidence and insight that customers want to further reduce resolution and therefore potentially “use Hyper-NA” NA The technology to mass-produce logic and memory chips already exists. This will be the change over the next decade or so. But it depends on the cost. "

An ASML spokesperson told Bits&Chips that the technical and economic feasibility of hyper-NA technology is being studied, but a decision has not yet been made on whether to proceed. He declined to comment on when the decision would be made. Considering the 2030 time frame mentioned by Van den Brink and the years of preparation required to develop a new generation of EUV scanners, it is not unreasonable to expect an early commitment. High numerical aperture technology was approved in 2015, well before low numerical aperture EUV was introduced into high-volume production.

By 2030, chipmakers may require high numerical aperture dual patterning, at least for a select number of layers. Meanwhile, scaling is expected to continue until at least 2036, according to a roadmap presented by Imec last year. This highlights the potential opportunities for a new generation of EUV scanners, provided cost targets can be met.

As early as 2022, Van den Brink expressed doubts about the economic viability of Super NA. “If the cost of super numerical aperture increases as fast as the cost of high numerical aperture, it’s almost not economically viable,” he told Bits&Chips, adding that his company is exploring solutions to keep the technology Controllability in terms of costs. and manufacturability. At the 2022 ASML Investor Day, Van den Brink expressed optimism that his engineers will succeed. “I’ve always believed in technology, so I’m confident we’ll get there.”

In April 2023, Van den Brink became even more confident in the Hyper NA business case. "I have traveled around the world many times to discuss the needs and desires of hyper-NA with customers. In recent months, I have gained the confidence and insight that customers want to further reduce resolution in order to mass-produce logic and memory chips using hyper-NA The opportunity already exists.”

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