The secret of SK Hynix’s 300+ layers of flash memory

Latest update time：2024-01-01

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Source: Content compiled from SK Hynix by Semiconductor Industry Observer (ID: icbank) , thank you.

At the Flash Memory Summit (FMS) 2023 in August, SK Hynix announced the world's first NAND flash memory sample with more than 300 layers. 321-layer 1 Tb TLC 4D NAND is another record-breaking latest 4D NAND solution since SK Hynix released its first 96-layer 4D NAND in 2018. These feats are enabled by the company's 4D ^2.0 NAND technology, which improves on proven technology to reduce chip size and increase layer count while increasing reliability and productivity.

In this article, we will introduce SK Hynix's advanced 4D NAND technology. These include 4D ^1.0 technologies that specialize in stacking and performance improvements , such as cost-effective 3-Plug structures, Sideway Source, and All Peri. 1 Under Cell (PUC) and Advanced Charge Trap Flash (CTF). It will also cover 4D 2.0 NAND technologies that overcome stacking limitations, such as multi-site cells (MSC).

NAND flash memory basics

In order to better understand 4D NAND technology, it is necessary to review the basic concepts and related terminology of NAND.

A cell is the smallest unit for storing information. In NAND flash memory, a cell consists of a control gate and a floating gate. When voltage is applied to the control gate, the electrons that pass through this path are stored in the floating gate. NAND flash stores data by using electrons stored on floating gates to classify cells as 0 or 1. This state is characterized by the number of electrons in the cell. For example, cells with fewer electrons are read as 0, while cells with more electrons are interpreted as 1.

NAND flash memory is divided into different types based on the amount of information (bits) stored in a single cell. These include single-level cells (SLC, 1 digit), multi-level cells (MLC, 2 digits), three-level cells (TLC, 3 digits), quadruple-level cells (QLC, 4 digits), and five-level cells (PLC, 5 Bit). As for the units used to measure NAND flash memory capacity, they include gigabytes (billions) and trillions (trillions). In other words, a TLC NAND flash product with a capacity of 1Tb has approximately 330 billion cells, each storing 3 bits.

4D ^1.0 technology: reducing chip size through unit stacking

SK hynix uses four major 4D ^1.0 NAND technologies to develop high-capacity NAND flash memory solutions.

1. Economical and efficient 3-plug structure

One of the key goals in developing semiconductor technology is to increase cost efficiency. This is achieved by stacking more units to reduce chip size and produce as many chips as possible on a single wafer. Stacking substrates layer by layer and repeating the cell formation process for each layer would be inefficient and increase manufacturing costs. So multiple layers of substrates are first stacked, then vertical holes called plugs are drilled into each layer, and cells are formed next to the holes.

As the number of layers increases, forming plugs on the bottom layer becomes more challenging because existing etching equipment can only etch about 100 layers at a time. Therefore, to develop NAND flash memory products with more than 300 layers, it is necessary to stack 100 layers and perform three plug etching processes. This is where using SK hynix's cost-effective 3-Plug molding comes in, as all processes including battery molding can be performed simultaneously on all layers.

As a result, SK Hynix can simultaneously manufacture the key structures of applied voltage and electron channel - word line 2 and word line ladder 3 through a single process. This enables the company to launch the highest density 321-layer 4D NAND in August 2023 while minimizing costs.

2. Sideway Source

Semiconductor plugs provide a transmission path for electrons. Inside the plug, this passage is covered by a CTF film 4. Therefore, it is necessary to remove the CTF film at the intersection of the plug and the bottom of the NAND flash layer to connect the two paths. Side source connect the plug to the bottom of the NAND flash layer (channel and source line 5). Previously, etching gas was injected from the top of the plug to remove the CTF film at the bottom of the plug vertically. However, when stacking two or more plugs, the centers of the plugs are not aligned. This prevents the etching gas from reaching the bottom and thus damaging the CTF film that serves as the plug side of the cell.

SK hynix solved this problem by replacing the vertical connection with a horizontal connection. The etching gas is injected into a separate channel to reach the bottom of the NAND layer and remove the CTF film on both sides of the plug.

With Sideway Source technology, the etching gas is not injected directly into the plug. Therefore, even if the plug is misaligned, there will be no damage inside. As a result, SK hynix significantly reduced defect rates, improved productivity, and resolved the cost increase associated with multiple stacks.

Since SK Hynix launched the industry's first 4D NAND in 2018, it has enhanced its expertise in producing precise horizontal path connections that leave no gaps at the bottom of the NAND layer. Based on this advancement, the company's 238-layer NAND flash memory production efficiency increased by 34% compared with 176-layer products, and further consolidated its market-leading position in 321-layer NAND.

3. All Peri. Under Cell (PUC)

PUC reduces chip size and increases stack count by placing peripheral circuits below the unit. SK hynix used PUC to develop a new NAND flash memory structure, the world's first 4D NAND, and then started product development. The company has further developed PUCs with its All PUC technology, enabling peripherals to be miniaturized. So it becomes the same as the cell size or smaller to accommodate the reduced cell size. In order to advance technological progress, SK hynix is further miniaturizing Peri. By reducing the size and number of transistors and adequately placing the perimeter. in the empty space below the cell.

In particular, this technology was applied to SK Hynix’s 238-layer 512Gb TLC NAND for the first time and achieved remarkable results. For this solution, the company reduced the size of the chip and peripherals. Compared with the previous generation product, it has increased by more than 30%, thereby improving production efficiency and cost competitiveness. SK hynix will continue to enhance its expertise and refine its technology to apply it to future products that require smaller peripherals and chips.

4. Advanced Charge Trap Flash (CTF: Advanced Charge Trap Flash)

Advanced CTF minimizes data degradation by retaining more electrons than traditional CTF. In CTF, electrons are stored in non-conductors rather than in conductors such as floating gates. Therefore, part of the purpose of developing CTF was to solve inter-cell interference in conductors by changing the electron storage space to a non-conductor. However, electrons often escape from non-conductors because they are stored in the voids of CTF materials (nitrogen-silicon compounds) which have unstable regions. When electrons are stored in these unstable regions, chemical bonds quickly break and the electrons are ejected, resulting in data loss.

For its advanced CTF, SK Hynix fills unstable areas with hydrogen to prevent electrons from entering, and increases the amount of binder to store more electrons. Additionally, Advanced CTF increases the number of electrons stored in the CTF by minimizing the risk of escaped electrons. This improves the ability to determine electron counts, reduces read errors, and significantly reduces latency.

When there are fewer electrons, some types of NAND flash have difficulty distinguishing data, causing errors. For example, if SLC flash memory uses 10 electrons to distinguish data, the data from 1 to 5 electrons will be 0, and the data from 6 to 10 electrons will be 1. However, if 5 electrons escape, the data previously processed as 1 will be distorted and an error will occur. This problem becomes more severe when cells are segmented to the MLC level or higher.

TLC distinguishes eight states from 000 to 111. If 10 electrons are to be distinguished, each state is assigned one or two electrons. This is significantly different from SLC, which assigns 5 electrons to each state. Therefore, even a few electrons escaping can cause data corruption.

Instead, consider the case of using Advanced CTF to differentiate data with 100 electrons. If the number of electrons is between 0 and 50, the data read is 0, and if it is between 51 and 100, it is read as 1. Even if some electrons escape, the overall number of electrons is larger, which greatly reduces the chance of misreading. data. Since there are fewer errors, latency is reduced and read speeds are increased.

SK Hynix applies Advanced CTF to its 176-layer NAND solution for the first time, improving the ability to determine electron counts by 25%. Because advanced CTF-based memory solutions have lower latency, they are particularly suitable for gaming and automotive markets that require fast data processing.

4D ^2.0 Technology: Increased horizontal cell density and stacking for enhanced performance and density

When developing semiconductor memory, manufacturing costs continue to rise with each additional layer. Given the additional cost of adding bits beyond TLC levels, a point has been reached where cost reduction is no longer possible. To this end, SK hynix is developing 4D ^2.0 technology, which increases the number of layers and horizontal density of cells to improve storage capacity relative to cost. Multi-site cell (MSC) is a 4D2.0 technology that structurally increases horizontal density, thereby significantly increasing the number of bits.

1. Multi Site Cell (MSC: Multi Site Cell)

There are two main methods for horizontally scaling cell density. The first is multi-level cell (MLC) technology, which subdivides the electron count to fit more data (bits) in a single cell. This is the case with NAND flash memory types from SLC to QLC. The second is MSC technology, which structurally increases the number of locations where electrons are stored in the cell, allowing it to accommodate more data (bits).

MLC technology has been commercialized in 4-bit QLC products, but maintaining performance and reliability in 5-bit and higher PLC products is challenging. This is due to the previously mentioned limitations in determining the electron count.

For example, if you use MLC to build a 6-bit six-level cell (HLC), you need to store data in 64 different states from 000000 to 111111. This is error-prone and time-consuming because there are not enough electrons to distinguish each state. Compared to 4-digit QLC, the ability to determine the number of electrons is four times worse.

On the other hand, when developing HLC using MSC, 8 states from 000 to 111 are created in two spaces and multiplied to achieve 64 states to store data. Doubles the ability to differentiate electron counts compared to 4-digit QLC. In other words, it has the capacity of an HLC but the speed of a TLC. SK hynix has confirmed that read and write speeds can be increased by 20 times when using MSC. Due to MSC's high capacity, high speed and reliability, SK Hynix's NAND flash memory is the leading solution for future multi-mode AI.

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