Intel's big bet: launching two new technologies at once

Intel has lagged behind TSMC and Samsung in advanced chip manufacturing over the past five years. Now, in an effort to regain its lead, the company is taking a bold and risky move, introducing two new technologies in desktops and laptops with Arrow Lake processors set to launch in late 2024. Intel also hopes to leapfrog rivals with new transistor technology and the first power delivery system.

Chris Auth, Intel's vice president of technology development and director of advanced transistor development, said that Intel has led the way in major changes in transistor architecture over the past two decades. However, the company's chip production has had a rocky past: In 2018, Intel failed to deliver its first 10-nanometer CPU on time, and production of the chip was delayed by a year, resulting in a shortage of CPUs built using its 14-nanometer chip. In 2020, the 7nm node (renamed Intel 4) was delayed again. The company has been playing catch-up ever since.

According to reports, Intel's upcoming nanosheet transistor RibbonFET will replace today's FinFET technology. FinFET transistors provide CPUs with lower power requirements and higher logic circuit density by wrapping the transistor's gate around the channel area from three sides instead of one. But as FinFET sizes shrink, these devices are approaching the limits of their gate's ability to control current. Nanosheet transistors, such as Samsung's multi-bridge channel FETs, offer better control because their gates completely surround the channel area. Intel expects that the introduction of RibbonFET into its upcoming Intel 20A processing node, the company's latest semiconductor manufacturing process technology, will improve energy efficiency by up to 15%. The "A" in 20A refers to angstroms, but, like the "nanometer" in previous chip naming conventions, it no longer refers to a specific measurement in the product.

The introduction of a new power supply scheme (commonly known as backside power supply, Intel calls it PowerVia) is a more significant change. “Ever since Robert Noyce made the first integrated circuit, everything has been on the interconnect front,” Auth said. This will be the first time a manufacturer has used a surface on the other side of the wafer to separate power from processing. This decoupling is important because power and signal lines are optimized differently: while power lines perform best on low-resistance, high-gauge wire, signal lines require more space between them to ensure minimal interference .

"This is a new playground," said Julien Ryckaert, vice president of logic technology at Imec. The move to nanosheet technology is traditional, but Ryckaert foresees opportunities to enable innovative new capabilities with backside power supplies.

Intel decided to launch both technologies at the same time about five years ago, around the same time it lost its lead over competitors. Typically, these types of projects take up to ten years. As Intel gets closer to implementing new transistors and power delivery networks, its executives are finding those timelines will intersect. So, in order to stay ahead of its competitors and avoid waiting for the next node to introduce one or the other, the company decided to pair these technologies. Both are seen as "key" to Intel's ambitious goal of regaining leadership in processing technology by 2025, Auth said.

"Intel used to be conservative," said Dan Hutcheson, vice chairman of TechInsights. Previously, TSMC was more aggressive in taking risks and had a higher chance of failure. That has now changed, Hutcheson explained. "Trying to implement two major technological changes at the same time is a very risky move, and in the past this has often led to disaster," he said.

Hutcheson added that Intel's innovation needs to be enabled by reliable production to attract and retain customers, especially as it continues to shift its business toward a semiconductor foundry model by separating manufacturing and product groups. He said that in the foundry model, it is crucial for customers to trust the manufacturer. Because of the long-term investment from development to delivery of the product, customers are "essentially betting on the farm for about two years".

Given the setbacks and delays Intel has experienced with the 10nm node, company executives are well aware of the risks they are taking. Ott said that while the industry is "built on risk-taking," "in this case, we took too much risk and we certainly recognized that mistake."

Therefore, to reduce the risks involved with the upcoming 20A node, Intel added an internal node that pairs PowerVia with current generation FinFETs. According to test results published in June 2023, adding PowerVia alone resulted in a 6% performance improvement. This internal stepping stone allows the company to test backside power delivery and iron out any issues with process and design.

On the process side, for example, Intel needs to figure out how to properly align and connect the front and back of the chip using nanometer-sized vertical connectors called through-silicon vias, which are 1/500 the size of previous connectors. Another challenge, Auth said, is maintaining the flat surface required for chip patterning when processing both sides of a silicon wafer.

Mark Horowitz, a professor of electrical engineering at Stanford University, said it's worth considering the projected cost given the higher requirements for manufacturing precision. Historically, as manufacturers adopt better technology, the cost per transistor falls. These cost improvements have now generally stabilized. "Transistors don't get priced as fast as they used to," Horowitz said.

At the same time, designers must rethink interconnect lines and layout. By using PowerVia to move the power lines to the back of the chip, Auth said, "you're undoing about seven years of front-end interconnect learning." For example, engineers have to relearn how to find defects and dissipate heat properly. Despite the steep learning curve, Intel expects the combination of new technologies to deliver significant benefits.

Imec's Ryckaert said that as each advancement addresses independent aspects of scaling, the new transistors and power delivery networks can be viewed as complementary. He suspects Intel's decision to introduce backside power during the FinFET-to-nanosheet transition was an attempt to attract customers by offering more significant benefits than either advancement could bring on its own. Nanosheet transistor technology may not be available for generations to come. “Soon, we will see saturation of nanosheets,” Ryckaert predicts.

Intel expects to have the 20A ready for production in the first half of 2024. TSMC plans to start producing chips using its N2 nanosheet technology in early 2025. Production of N2P chips (versions with backside power supply) is expected to begin in 2025. 2026. Samsung has introduced nanosheet transistors in its 3nm node in 2022, but has not officially announced a timetable for implementing backside power.

Hutcheson believes that all chipmakers are on the same path toward backside power. Intel is just the first to take this step. If the company succeeds, the risk could allow it to regain its leadership position, he said. "It's a lot of things."

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