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Lu Xingzhi: TSMC's 3nm process may be a failure

Latest update time:2022-07-05
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TSMC has become the epicenter of the Taiwan stock market. TSMC will hold an earnings conference on July 14. Well-known semiconductor analyst Lu Xingzhi said that TSMC is being sold off at an accelerated pace by foreign investors. It seems that the 3-nanometer process that will be mass-produced in the second half of the year is a big failure. Don't waste time on the second quarter figures on July 14. Investors should be more concerned about four major issues, including long-term revenue growth targets, customer order delays, production utilization, and gross profit margins.


Foreign capital is withdrawing funds from TSMC without stopping. Lu Xingzhi said that it seems that even if TSMC is being sold off at a low price by foreign capital at an accelerated pace, the company will not announce a change in the short-term revenue growth trend. The sharp increase in capital expenditure will pose a risk to profit margins after the decline in capacity utilization.


Lu Xingzhi also rarely pointed out that TSMC's 3nm process (N3), which will be mass-produced in the second half of this year, seems to be a major failure. It is obviously delayed by half a year compared to the mass production schedule of 5nm and 7nm. Not only will Apple be unable to adopt it in its new mobile phones to be launched in September, but at last week's technical forum, it seemed that TSMC simply omitted the 3nm process and directly compared the upgraded version of 3nm (N3E) with 5nm.


If the upgraded version of 3nm is the main 3nm product contributing to TSMC's revenue in 2023, it means that the upgraded version of 3nm is at least one year longer than the previous advanced process. It is no wonder that 2nm will be delayed until the second half of 2025 for mass production and shipment, giving competitors a year of breathing space.


The market is paying attention to TSMC's July 14th earnings conference, but Lu Xingzhi pointed out that investors should not waste time on the second quarter figures. Investors should be more concerned about four major issues: long-term revenue growth targets, customer order delays, production utilization, and gross profit margins:


1. Will TSMC's revenue growth in 2023-2024 be lower than the previously provided 15-20% CAGR target? Will it be revised down? If the target remains unchanged, will the company factor in the significant impact of customers' inventory reduction and global inflation/stock market crash on technology products and semiconductor demand, rather than relying on customers' orders that can be delayed and canceled to expand production and tell investors.


2. Does TSMC have any penalties or loss-sharing mechanisms for major customers who delay or cancel long-term orders?


3. The capacity utilization rate of 12-inch advanced process, 12-inch mature process, and 8-inch special process will have to decline to a certain extent before the company will consider putting the brakes on capital expenditure.


4. Assuming all other assumptions remain unchanged, if the capacity utilization rate drops by 10% or 20%, how much impact will it have on the company's gross profit margin?


Goldman Sachs Securities pointed out that although 2023 looks challenging, facing demand uncertainty, inflation and the high base test in 2022, TSMC is expected to deliver excellent performance through the smooth mass production of 3nm process and price increase strategy. Regarding the upcoming earnings conference, Goldman Sachs put forward the following key points for observation:


1. What is TSMC’s view on terminal demand, especially in the field of high-performance computing (HPC), and the long-term growth expectations of the entire semiconductor industry (excluding memory) in an inflationary environment.


2. TSMC is expected to release more details on its production expansion, and we look forward to TSMC's latest observations on the supply and demand situation of mature processes.


3. TSMC's 3nm process will enter risk trial production at the end of 2021, and mass production is scheduled for the second half of the year. However, there are delays in the supply of semiconductor equipment. What potential impact will it have on TSMC?

N3: Five nodes in the next three years


As manufacturing processes become more complex, their pathfinding, research, and development times become longer, so we no longer see a completely new node every two years from TSMC and other foundries. In N3, TSMC's new node introduction cadence will expand to about 2.5 years, and in N2 it will extend to about 3 years.


This means TSMC will need to offer enhanced versions of N3 to meet the needs of its customers, who are still looking for improvements in performance per watt and transistor density every year or so. Another reason TSMC and its customers need multiple versions of N3 is that the foundry's N2 relies on a completely new gate-all-around field-effect transistor (GAA FET) implemented using nanosheets, which is expected to bring higher costs, new design methods, new IP, and many other changes. While developers of cutting-edge chips will quickly move to N2, many of TSMC's regular customers will stick with various N3 technologies for the next few years.



At its 2022 TSMC Technology Symposium, the foundry talked about four N3-derived manufacturing processes (for a total of five 3-nanometer-class nodes) that will be launched in the coming years - N3E, N3P, N3S, and N3X. These N3 variants are designed to provide improved process windows, higher performance, increased transistor density, and enhanced voltage for ultra-high-performance applications. All of these technologies will support FinFlex, TSMC's "secret weapon" feature that greatly enhances their design flexibility and allows chip designers to precisely optimize performance, power consumption, and cost.


*Note that TSMC only started releasing transistor density enhancements for analog, logic, and SRAM separately around 2020. Some of these numbers still reflect a “mixed” density consisting of 50% logic, 30% SRAM, and 20% analog.

*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.


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