India is focusing on RISC-V processors

Source: This article is from cnx-software , thank you.

One of the main advantages of the RISC-V architecture is that it is open, so any organization with the right skills can develop its own core, and the Indian government seized this opportunity using the Microprocessor Development Program (MDP) to help develop the VEGA RISC-native V core.

With funding from the Ministry of Electronics and Information Technology (MeitY), the Centre for Development of Advanced Computing (C-DAC) has successfully designed five RISC-V processors, ranging from a single-core 32-bit RISC-V microcontroller-class processor to a quad-core 64-bit out-of-order processor with Linux support.

Key features of the five VEGA cores developed by C-DAC:

• VEGA ET1031 – 32-bit single-core 3-level in-order RV32IM processor with AHB/AXI4.bus, optional MMU, optional debug

• VEGA AS1061 – 64-bit single-core 6-level in-order RV64IMAFDC processor with 8KB D-cache, 8KB I-cache, FPU, AHB/AXI4 bus

• VEGA AS1161 – 64-bit single-core 16-stage pipelined out-of-order RV64IMAFDC processor with 32KB D-cache, 32KB I-cache, FPU, AHB/AXI4/ACE bus

• VEGA AS2161 – 64-bit dual-core 16-stage pipelined out-of-order RV64IMAFDC processor with 32KB D-cache, 32KB I-cache, 512KB L2 cache, FPU, AHB/AXI4/ACE bus

• VEGA AS4161 – 64-bit quad-core 16-stage pipelined out-of-order RV64IMAFDC processor with 32KB D-cache, 32KB I-cache, 1024KB L2 cache, FPU, AHB/AXI4/ACE buses

Take a closer look at the key features of the high-end VEGA AS4161:

RISC-V 64G (RV64IMAFD) instruction set architecture

· 13-16 stage out-of-order pipeline implementation

Advanced branch predictors: BTB, BHT, RAS

Harvard architecture, independent instruction and data memory

User, Supervisor, and Machine mode permission levels

Fully functional memory subsystem supporting Linux

Memory Management Unit

Page-based virtual memory

Configurable L1 cache ​

Configurable second-level cache

High-performance multi-core interconnect

High-performance floating-point unit compliant with IEEE 754-2008

AXI4- / ACE-compatible external interface

Platform-level interrupt controller

Up to 127 IRQs

Low interrupt latency

Vectored interrupt support

Advanced Integrated Debug Controller

JTAG compatible interface

Hardware/software breakpoint support

· Debug extension allows Eclipse debugging via GDB >> openOCD >> JTAG connection

Linux compatible

Desktop Linux processors are not expected anytime soon, as the AS4161 is primarily targeted at storage and networking applications.

Even better is the public availability of documentation for two SoCs (THEJAS32 and THEJAS64), based on the VEGA ET1031 and VEGA AS1061 cores respectively, with HDL code running on an ARTYA7 FPGA board (A7-35T can run THEJAS32, but A7-100T is required for THEJAS64). A C/C++ VEGASDK with Eclipse IDE allows engineers to develop programs for the platform, and Linux source code for 64-bit VEGA processors is also available . The code is hosted on Gitlab , but you need to request access before retrieving the code... which is a bit disappointing.

The Indian government also plans to hold training courses for VEGA processors, but the page is currently empty. No information can be found about VEGA's timeline and whether manufacturing will be planned in India. The project's blog has not been updated for several months, but the "VEGA Processors" YouTube account uploaded a video on January 31, 2022, providing an overview of the five VEGA RISC-V processors.

More details can be found on the project website (https://vegaprocessors.in/).