Choices after 3nm
Latest update time：2021-12-29 17:23
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In three days, the "Moore's Law" regarded as a golden rule by the semiconductor industry will enter its 57th year. At the same time, it will also enter another year of "death". Since Moore's Law was first proposed in 1965, global chip technology has basically been operating under this principle, and it has witnessed the pace of human information technology advancement.
Looking back, since the beginning of this century, industry leaders have been predicting that Moore's Law will "die." The 2004 revision of the International Technology Roadmap for Semiconductors (ITRS) predicted that the linear development of Moore's Law might continue for 10-15 years.
In 2013, the Defense Advanced Research Projects Agency of the United States Department of Defense believed that 7 nanometers would be the final process node for chips in 2020. Robert Crowell, director of its Microsystems Technology Office, said that the chip industry is expected to spend a lot of effort to promote the 5 nanometer process, which will postpone the original end of Moore's Law to 2022. In 2015, Henry Samueli, chief technology officer of Broadcom, said: "Moore's Law has become gray and faltering. It is not dead yet, but it is time to retire."
Under the invisible sword of "Moore's Law is dying", the global semiconductor industry has experienced year after year, and now the chip process node has reached 3nm. Global researchers are also "hanging a sword over their heads" and constantly exploring new materials, new transistors, new equipment and other fields to meet the challenges of future chips.
Two-dimensional materials are expected to transform traditional integrated circuit architecture
As we all know, the original material of the wafer is silicon. As a semiconductor, silicon can be adjusted to be a good conductor or insulator by introducing a small amount of impurities. However, as the manufacturing process of integrated circuits has entered below 5nm in recent years, the size of transistors has continued to shrink and approach its physical limit, and traditional silicon-based materials are increasingly unable to support the further development of integrated circuit performance.
Two-dimensional materials are a new type of material developed since 2004, represented by transition metal chalcogenides (TMDCs), including transition metal dichalcogenides (TMDs) with the general formula MX
2
, where M is a transition metal (e.g., Mo or W) and X is a chalcogen element (e.g., S, Se or Te). This material has the characteristics of extreme thickness, high mobility and back-end heterogeneous integration, and is expected to change the architecture of traditional integrated circuits, and has attracted the attention of academia and industry.
At present, Intel, Samsung, TSMC and other major chip technology companies have already laid out this field. In order to cope with the future chip crisis, Europe is also committed to the research and development of two-dimensional materials such as graphene. In addition, my country's Peking University and Nanjing University have also made technological breakthroughs in this field.
-
Intel - MoS₂ solves the physical limitations of traditional silicon chips
Recently, at the 2021 IEEE International Electron Devices Meeting (IEDM), Intel announced three new technologies that break Moore's Law. The goal of these technologies is to enable chip technology to continue to develop after 2025, and two-dimensional materials are mentioned among them.
It is understood that Intel proposed to use a two-dimensional material called TMD (transition metal sulfide) instead of silicon as a current channel. The characteristic is that there is a very thin, single-layer disulfide atomic layer under the channel, which can serve as a shorter channel.
Lu Donghui, vice president of Intel's Manufacturing, Supply Chain and Operations Group and co-general manager of the Strategic Planning Department, pointed out, "The problem with silicon is that it cannot be shrunk any further. If it is shrunk any further, many quantum effects will appear. However, two-dimensional materials have their own characteristics, so they can be made very small." Intel's biggest breakthrough in materials is the use of two different metals to make metal contacts. NMOS uses antimony and PMOS uses ruthenium, which can make the capacitor smaller.
Intel said that applying a single layer of molybdenum disulfide MoS₂ to the connection layer of silicon chips can reduce the spacing from 15nm to 5nm, solving the physical limitations of traditional silicon chips.
-
TSMC--- MoS2 combined with bismuth achieves extremely low contact resistance
TSMC, in collaboration with National Taiwan University and the Massachusetts Institute of Technology, has discovered that two-dimensional materials combined with semi-metallic bismuth can achieve extremely low contact resistance, close to the quantum limit. This research finding was published in the journal Nature in May this year.
It is understood that due to the limitations of high resistance and low current, two-dimensional materials such as graphene have not been able to replace silicon-based semiconductors. The MIT team first discovered that the combination of molybdenum disulfide (MoS
2
) and semi-metallic bismuth can effectively reduce resistance and improve current transmission efficiency. TSMC's technology research department then optimized the bismuth deposition process, and finally the NTU team used the helium ion beam lithography system to successfully shrink the component channel to the nanometer level, and finally came to this research result.
As early as March last year, TSMC and National Chiao Tung University in Taiwan jointly developed the thinnest boron nitride two-dimensional insulating material, which is only 0.7nm thick and can be used for a breakthrough in the 1nm process.
-
Samsung--Discovered new material "amorphous boron nitride"
Last July, Samsung Electronics Institute of Technology announced that they had successfully discovered a new material, "amorphous boron nitride (a-BN)", in collaboration with Ulsan Institute of Science and Technology. According to reports, the research team not only ensured the world's lowest dielectric constant of 1.78, but also proved that the material can be produced on a large area on a semiconductor substrate at 400°C, thus taking a step towards process innovation. Amorphous boron nitride can be applied to semiconductor systems including memory semiconductors (DRAM, NAND, etc.), and is expected to be used in memory semiconductors for servers that require high performance.
In fact, Samsung has been researching two-dimensional materials for many years. In 2012, Samsung used graphene to develop a new transistor structure; in 2014, Samsung solved the limitation that graphene semiconductor wafers could not be generated, formed the world's first pure graphene layer on the wafer, and developed source technology for large-scale production; in 2017: Samsung got rid of the regular hexagonal grid structure of existing graphene, developed a graphene structure in which carbon atoms were connected in a random form, and successfully synthesized it on a large scale.
-
EU--Committed to the research and development of two-dimensional materials
In order to cope with the future chip crisis, Europe is also committed to the research and development of two-dimensional materials such as graphene. As early as 2013, the European Union invested 1 billion euros to promote the development of graphene technology in the next 10 years. In the past year, three experimental production lines of graphene materials have been put into operation.
Earlier this year, a new experiment from the EU's Graphene Flagship Project proposed a new method for integrating graphene and 2D materials into semiconductor production lines and published it in Nature Communications.
Image source: Nature
The researchers used a copper foil with a diameter of 100 mm as the growth substrate for chemical vapor deposition (CVD) of single-layer graphene, and a silicon wafer with an oxide layer (SiO
2
/Si) with a diameter of 1 cm as the growth substrate for molybdenum disulfide. They transferred these two materials to a silicon substrate with a diameter of 100 mm to improve the success rate of two-dimensional material transfer.
-
Peking University - Achieved epitaxial preparation of 2-inch single-layer single crystal WS 2
On November 15, Songshan Lake Materials Laboratory/Peking University Researcher Liu Kaihui, Academician Wang Enge's team and their collaborators published a research paper titled "Dual-coupling-guided epitaxial growth of wafer-scale single-crystal WS2 monolayer on vicinal a-plane sapphire" in Nature Nanotechnology. They proposed for the first time a new growth mechanism of "dual-coupling coordinated regulation" and successfully achieved the preparation of a 2-inch single-layer single-crystal tungsten disulfide (WS2) on a sapphire
substrate
.
Image source: Songshan Lake Materials Laboratory
After in-depth exploration, the research team proposed a new mechanism of "double-coupling coordinated regulation" of van der Waals coupling and step interaction between two-dimensional materials and insulating substrates, and realized the epitaxial preparation of 2-inch single-layer single crystal WS
2.
The key physical idea of the "double-coupling coordinated regulation" mechanism is that
the van der Waals interaction between
WS
2
and the sapphire substrate limits the dominant orientation of the WS
2
crystal domain to 0° and 180°; the interaction between WS
2
and the sapphire steps can break the energy degeneracy of the two orientations, so that the WS
2
crystal domain retains only one dominant orientation.
-
Nanjing University--Achieved epitaxial growth of 2-inch MoS2 single crystal thin film
Professor Wang Xinran's research group at the School of Electronic Science and Engineering of Nanjing University artificially constructed atomic-scale "terraces" by changing the direction of the atomic steps on the sapphire surface. Using the directional induced nucleation mechanism of the "atomic terraces", the directional growth of TMDC was achieved. Based on this principle, the team achieved the epitaxial growth of 2-inch MoS2 single crystal films for the first time in the
world
.
Image source: Nanjing University
Thanks to the improvement in material quality,
the field effect transistor mobility based on MoS2 single crystal is as high as 102.6 cm2
/
Vs
, and the current density is 450 μA/μm, which is one of the highest comprehensive performances reported internationally. At the same time, this technology has good universality and is suitable for the single crystal preparation of other materials such as MoSe2
.
This work has laid a material foundation for the application of TMDC in the field of integrated circuits.
New changes in transistor structure
As the process evolves step by step, the size of transistors is also shrinking little by little, so that more electronic components can be integrated into a given chip area, resulting in stronger system functions and exponentially lower costs. But now, "Moore's Law" is about to celebrate its 57th birthday, and the chip manufacturing process has entered the post-FinFET era. The number of transistors that can be packed into a single chip has almost reached its limit. There is no doubt that in addition to new materials, transistor structure will also usher in new changes.
-
GAA
Among the three new technologies announced by Intel to break Moore's Law, the improvement of transistor miniaturization area is one of them. It is reported that Intel will adopt GAA RibbonFET (Gate-All-Around RibbonFET) technology to achieve up to 30% to 50% improvement in logic miniaturization by stacking multiple (CMOS) transistors. The more transistors per unit area, the more powerful the semiconductor performance. RibbonFET is Intel's implementation of GAA transistors and the company's first new transistor architecture since it first launched FinFET in 2011.
The difference from FinFET is that GAA has gates around the four sides of the channel, which can reduce leakage voltage and improve control of the channel, which is key when shrinking the process node. Samsung has also announced that it will use GAA for 3nm process, which is expected to be put into production in 2022. In addition, TSMC Chairman Liu Deyin has also pointed out that after 2nm, TSMC will turn to the GAA architecture, which provides more electrostatic control than the FinFET architecture and improves the overall power consumption of the chip.
-
VTFET
At IEDM 2021, IBM and Samsung unveiled a new design for vertically stacking transistors on a chip, called VTFET. VTFET (Vertical Transfer Field Effect Transistor) places transistors perpendicular to the silicon wafer and directs current perpendicular to the surface of the silicon wafer. This new approach addresses scaling barriers by breaking the physical limitations on transistor gate length, spacer thickness, and contact size in order to optimize various parameters including performance and power consumption.
According to IBM and Samsung, this design has two advantages. First, it will allow them to bypass many of the performance limitations that keep Moore's Law alive beyond IBM's current nanosheet technology. More importantly, this design results in less energy waste due to the greater flow of current. They estimate that VTFET will make processors twice as fast or use 85% less power than chips designed with FinFET transistors.
Once VTFET technology matures, we will have to wait and see whether Samsung, which has announced the adoption of GAA technology, will use VTFET for advanced processes in the future.
-
CasFET
CasFET is a new type of transistor introduced by Purdue University engineers. It has a superlattice structure perpendicular to the transmission direction of the transistor. They behave like quantum cascade lasers rather than traditional FET devices, allowing the transistor to achieve lower switching voltage, lower power consumption, more dense design and smaller size.
Image credit: Purdue University
"The simulated quantum cascade laser switches its transport properties from coherent/ballistic to stepwise and phonon-assisted tunneling via an external electric field," said Tillmann Kubis, assistant professor of electrical and computer engineering at Purdue University. "This switching effect is what we add to the 'standard' field-effect switch of a FET."
Moreover, he adds, "CasFETs are more sensitive to the gate than state-of-the-art transistors, and this also applies to gate-all-around FETs. All of these transistors rely on a single switching mechanism. Ours has two." A prototype CasFET device is currently under design.
The next generation of EUV lithography machines must also be prepared
When it comes to future chip manufacturing processes, photolithography machines are obviously an indispensable topic. It can be said that process breakthroughs are to some extent restricted by photolithography machines. The essence of photolithography is actually a projection system. Light is projected through a mask and imaged on a wafer, and eventually complex transistors are built up layer by layer on the wafer. As photolithography technology continues to move towards a "smaller" journey, the next generation of photolithography machines also need to be adequately prepared.
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High-NA EUV
To avoid EUV double patterning, High-NA EUV has become the focus, which can achieve a simpler single patterning method. Lithography giant ASML will change from the current 0.33 NA to 0.55NA (i.e., NA increased by 67%) by redesigning the optical devices within the lithography system. 0.55NA EUV lithography is expected to eventually achieve 8nm resolution, corresponding to a printed line/pitch of 16nm pitch in a single exposure.
According to ASML's October report, its latest EUV lithography machine can help manufacturers cram more and more transistors onto silicon substrates in the next 10 years or so. ASML predicts that by 2030, there will be chips with 300 billion transistors integrated.
ASML reports that starting in 2023, ASML plans to deliver the first next-generation EUV equipment, which will go from 0.33 NA to 0.55 NA, making EUV numerical aperture (NA) higher than the capabilities of current machines. This will allow chipmakers to develop process nodes far beyond the currently expected 2 nm threshold, and also save some costs when using single-exposure EUV processes for advanced wafer layers.
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EUV Photoresist
The transition to high-NA lithography at future process nodes will require not only engineering innovation from system suppliers such as ASML, but also advanced development of suitable photoresist materials to continuously improve the performance of photoresists.
Lam Research will use a chemical vapor deposition process to layer on the metal photoresist, rather than wet photoresist technology. One of the biggest advantages of Lam Research's dry resist technology is that it uses a chemical vapor deposition (CVD) process to deposit the photoresist, which allows for finer control over the variability and thickness of the photoresist.
Tokyo Electron has discovered a new solvent wash process that can extend production lines to ~24nm (12nm critical dimension). This process may allow wet resist methods to be scaled to 24nm.
Tokyo Electron and JSR claim they have a new post-exposure bake process for metal oxide resists that will help improve the sensitivity of the photoresist.
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New Mask Types
In addition to photoresists, High-NA EUV requires new photomask types. To reduce the effects of unwanted pattern placement shifts, EUV masks require thinner absorbers. The thickness of the tantalum absorber in current EUV masks is 60nm, and although it can be made thinner, it is limited to 50nm and does not solve the mask effect. To this end, the industry is developing several new EUV mask types, such as 2D, absorber-free, high-k, non-reflective, and PSM.
In a presentation at the SPIE Photomask/EUV conference, Hanyang University researchers described a phase-shift EUV mask consisting of alternating layers of ruthenium and silicon on a substrate. A ruthenium capping layer sits on top of the multilayer structure, followed by a tantalum-boron etch stop layer, and a ruthenium alloy as the phase-shift material.
High-k masks are under development, and the industry is exploring other materials such as nickel to replace tantalum absorbers. It is understood that thinner nickel absorbers can reduce the mask effect, but at the same time they are difficult to use.
In addition, startup Astrileux also described a new non-reflective EUV mask using ruthenium. The company also said that 2D masks and others are in the works.
Final Thoughts
Technology may have its limits, but human wisdom has no limits. No one knows when "Moore's Law" will die, but as researchers continue to explore, perhaps it will be "extended" continuously, and the future chip crisis may be solved one day with the birth of a new technology.
Finally, I would like to quote Wang Chuan of Silicon Valley in his book “Why Moore’s Law Has Not Died, But People Continue to Predict Its Death”: “More money, more people, better tools, faster communications, and multiple solutions to increase transistor density are advancing in parallel. The best solution among these solutions will definitely continue to surpass the efficiency of previous solutions. But before the winner emerges, it is difficult for us to predict in advance which solution will win.”
*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.
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