AMD announces Zen 4 roadmap: 96 cores in 2022, 128 cores in 2023
Latest update time：2021-11-12 11:23
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AMD CEO Lisa Su shared the company's Zen 4 CPU roadmap today at its AMD Accelerated Datacenter event, including 96-core Genoa models and 128-core Bergamo chips. This came on the heels of AMD's unveiling of the EPYC Milan-X chip with up to 768MB of L3 cache and the Instinct MI250X GPU.
AMD also shared the first details of the 5nm TSMC process it will use for the new Genoa and Bergamo chips, claiming it offers twice the density and power efficiency and 1.25 times the performance compared to the 7nm process AMD uses for its current generation chips.
The new roadmap covers the fourth generation of EYPC processors. The 96-core Genoa will debut in 2022 using a 5nm process, while the 128-core Bergamo, also using a 5nm process, will be available in 2023. In addition, Bergamo is also equipped with a new type of "Zen 4c" core for specific use cases, which means that AMD's Zen 4 chips will be equipped with two types of cores, and the "c" core with the alarm function is obviously a smaller variant.
Here’s AMD’s TLDR for the Zen 4 CPU roadmap:
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“Genoa” will have up to 96 high-performance “Zen 4” cores, enabling next-generation memory and I/O technologies in DDR5 and PCIe Gen 5, and driving platform capabilities to perfectly balance Zen 4 cores, memory and I/O to deliver leading efficiency;
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"Bergamo" is a high-core-count compute engine tailored for cloud-native applications that require high thread density. It has 128 high-performance "Zen 4 C" cores;
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"Bergamo" has all the same features as Genoa, including DDR5, PCIe 5, CXL 1.1, the same RAS and full suite of Infinity Guard safety features, and is compatible with the Genoa socket
Genoa will use TSMC's 5nm process, which AMD says is twice as dense and power efficient as the 7nm process that powers the current generation of EPYC Milan chips. It also offers 1.25 times the performance of the 7nm process. This also bodes well for the consumer-focused Ryzen Zen 4 chips.
The EPYC Genoa chip will have up to 96 Zen 4 cores and support DDR5 and PCIe 5.0, as well as the CXL 1.1 interface that allows consistent memory connectivity between devices. The chip will address HPC and general data center, enterprise and cloud workloads, and Su said it will scale per-core and socket-level (multi-threaded) performance. Genoa is sampling to customers now and is expected to launch in 2022.
Bergamo is also manufactured using the 5nm process and will feature up to 128 cores in a single chip.
AMD has created a new "Zen 4c" type of Zen 4 core, with the "c" indicating that the core is designed for cloud-native workloads. The Zen 4c core debuted in the 5nm EPYC Bergamo, which is socket-compatible with Genoa and uses the same Zen 4 instruction set. This means you can put these chips in the same servers as the Genoa models.
These "c" cores are likely to be smaller than the standard Zen 4 cores that will debut at Genoa, with certain unneeded features removed to improve compute density. However, the chips feature a density-optimized cache hierarchy to increase the number of cores, thereby addressing cloud workloads that require higher thread density. This could mean the chips have smaller caches, or that cache levels may have been removed, but AMD hasn't shared details yet.
AMD does say that Bergamo will offer higher levels of power efficiency and performance per socket. Bergamo will ship in the first half of 2023. It has the same overall feature set as Genoa, so it has PCIe 5.0, DDR5, and CXL 1.1.
We'll surely learn more as AMD gets closer to launching these processors. Stay tuned.
AMD Zen 4 architecture details revealed
Recently, industry insider Hans de Vries exposed some CPU design architecture details of Zen 4, which are said to be confidential documents leaked to the black market after a major hardware manufacturer was attacked by ransomware not long ago.
The icon outlines the cache part of Zen 4. Compared with Zen3, the size of the first-level instruction/data cache has not changed, it is still 32KB and 8-way associated, but the second-level cache (instruction + data) has doubled from 512KB to 1MB, and it is still 8-way associated.
Unfortunately, the capacity of the third-level cache has not been announced. It seems there will be a surprise. The previous generation Zen3 shared 32MB for each CCD (8-core Die).
However, in comparison with the 12th generation Core Alder Lake system, Golden Cove (P core, performance core) has 1.25MB of L2 cache per core, while Gracemont (energy efficiency core, E core) has 2MB for every four cores, which means that the maximum L2 cache is 14MB. This means that Zen4's physical 16 cores (16MB L2) will surpass again.
Generally speaking, the first and second level caches play an extremely important role in branch prediction, and they are also an important support for the increase in IPC indicators. According to AMD's previous statement, the change in Zen4 to Zen3 will not be less than that of Zen3 to Zen2, the latter of which increased its IPC by 19% at the time. The 5nm Zen4 is very promising, and there is also the advantage of being a latecomer.
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