RISC-V has developed rapidly in the past year

Latest update time：2021-09-03 12:13

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Recently, RISC-V International CE0 Calista Redmond emphasized in a press release that RISC-V has achieved incredible growth and momentum in the past year. She further pointed out that in the past year, we have seen the growth momentum of RISC-V cores, SoCs, development boards, software and tools in the market across the entire computing field from embedded to enterprise. "

“We are proud of our growing global membership, which has more than doubled in the last year to 1,000 members, including 222 organizations,” said Calista Redmond.

The press release further states that in 2020, RISC-V continues to focus on driving progress and development of standards and technical deliverables. In March, the RISC-V Processor Trace Task Group approved the Processor Trace Specification, a new standard trace encoder algorithm that allows engineers and developers to step through and see the exact core instructions.

The RISC-V Technical Steering Committee (TSC) is focused on implementing organizational governance practices to increase transparency. The RISC-V Architecture Test Working Group initiated a compatibility framework and conducted tests to help developers ensure their solutions comply with the specification.

Additionally, RISC-V International and GlobalPlatform, a standards organization for secure digital services and devices, announced a partnership to help accelerate the development of open standards that simplify secure design for hardware developers and enhance the security of Internet of Things (IoT) devices and processors.

According to the press release, RISC-V is expected to conduct public review of its Vector, Bit Manipulation, Scalar Cryptography, Packed SIMD, Secure PMP and Virtual Memory extensions in the first quarter of 2021. RISC-V has also created a security response process to better respond to potential security issues and adopt innovative cryptographic extensions to enhance performance in secure deployments.

RISC-V International has also established alliances with 16 different regional and industry organizations to ensure collaboration across all boundaries and interests. Three projects have been launched, including: the Chinese Academy of Sciences and PLCT Laboratory are working on the Low Level Virtual Machine (LLVM) and GNU Compiler Collection (GCC) projects to obtain unprivileged instructions; Shakti and IIT Madras are conducting architectural testing of unprivileged instructions; RISC-V International Open Source Laboratory (RIOS Lab) is conducting formal models and architectural testing for unprivileged instructions.

In June 2020, RISC-V International appointed Mark Himelstein as CTO to work with the RISC-V technical community to understand, define and lead strategic imperatives extending from ISA to software and from embedded to high-performance computing (HPC). The organization also appointed Kim McMahon as Director of Marketing, further expanding its leadership team to increase awareness of RISC-V and extend the member community's growing industry momentum. RISC-V International also announced RISC-V Tier 1 Ambassadors this year. Ambassadors are RISC-V technical experts from around the world who share RISC-V's commitment to engaging engineers around the world in technical forums.

“RISC-V has been focused on approving extensions, identifying and addressing opportunities and gaps, and expanding collaboration and development across the market to enhance the community and access to RISC-V resources,” said Himelstein. “In 2020, we expanded the number of technical groups, formed new alliances, and launched new educational programs to help achieve this goal, and will continue to redouble our efforts in the coming years to help drive volume deployment of RISC-V.”

Zurich – December 8, 2020 – RISC-V International, the non-profit corporation controlled by its members to drive adoption and implementation of the free and open RISC-V instruction set architecture (ISA), highlighted an incredible year of growth for the organization during RISC-V International CEO Calista Redmond’s keynote address today at the RISC-V Summit, taking place December 8-10, 2020. This year RISC-V International has made significant progress on its technical deliverables, launched new educational initiatives, expanded its leadership team and member base, and continues to see strong commercial adoption.

RISC-V has seen incredible growth and momentum. This year, our technical community has grown 66% to over 2,300 individuals in more than 50 technical and special interest groups. We are seeing momentum in the market for RISC-V cores, SoCs, development boards, software, and tools across the computing spectrum, from embedded to enterprise,” said Steve Jobs, CEO of RISC-V. “We are proud of our growing global membership, which has more than doubled in the last year to 1,000 members, including 222 organizations.”

In 2020, RISC-V continued to focus on driving progress and closure on standards and technical deliverables. In March, the RISC-V Processor Trace Task Force approved the Processor Trace Specification, a new standard trace encoder algorithm that allows engineers and developers to step through and see the exact core instructions. The RISC-V Technical Steering Committee (TSC) focused on implementing organizational governance practices to increase transparency. The RISC-V Architecture Test Working Group initiated a compatibility framework and testing to help developers ensure their solutions meet the specification. In addition, RISC-V International and GlobalPlatform, the standard for secure digital services and devices, announced a partnership to help accelerate the development of open standards that simplify secure design for hardware developers and enhance the security of Internet of Things (IoT) devices and processors. RISC-V is on track to have our vector, bit processing, scalar crypto, packed SIMD, secure PMP, and virtual memory extensions available for public review in the first quarter of 2021. RISC-V has also created a security response process to better respond to potential security issues and adopt innovative cryptographic extensions to enhance performance in secure deployments.

RISC-V International has established alliances with 16 different regional and industry organizations to ensure collaboration across all boundaries and interests. Three projects have been launched, including: the Chinese Academy of Sciences and PLCT Laboratory are working on the Low Level Virtual Machine (LLVM) and GNU Compiler Collection (GCC) projects to obtain unprivileged instructions; Shakti and IIT Madras are conducting architectural testing of unprivileged instructions; RISC-V International Open Source Laboratory (RIOS Lab) is conducting formal models and architectural testing for privileged instructions.

In June 2020, RISC-V International appointed Mark Himelstein as CTO to work with the RISC-V technical community to understand, define and lead strategic imperatives extending from ISA to software and from embedded to high-performance computing (HPC), with all members’ interests in mind. The organization further expanded its leadership team with the appointment of Kim McMahon as Director of Marketing to increase awareness of RISC-V and extend the member community’s growing industry momentum. RISC-V International also announced this year its first class of RISC-V Ambassadors. Ambassadors are RISC-V technical experts from around the world who share RISC-V’s commitment to engaging engineers around the world in technical forums.

RISC-V International has launched three new learning programs, including the RISC-V Training Partner Program, Online Learning, and University Alliance, to expand the breadth and scope of RISC-V knowledge, providing opportunities for a broad audience to teach and learn, participate in the community and gain expertise in key areas required for a healthy ecosystem. One of the recently released courses is the Imagine University Program (IUP) course "RVfpga: Understanding Computer Architecture". The course is currently available in English and will be available in Chinese in early 2021. Students and developers interested in RISC-V can also view more than 30 educational courses RISC-V provides from universities and other education providers around the world.

This year, the RISC-V community continued to contribute to the RISC-V project, collaborate together and commercialize RISC-V hardware and software solutions. RISC-V also launched the RISC-V Exchange, which features more than 124 RISC-V cores, SoCs and development boards and 129 RISC-V software applications and tools.

Notable examples of RISC-V adoption in 2020:

Alibaba has unveiled its RV64GCV core, which will be used in its Xuantie 910 processor aimed at cloud and edge servers.
Andes announced new superscalar multicore processors and processors with Level-2 (L2) cache controllers.
BBC Learning and Tynker have released BBC Doctor Who HiFive Inventor.
Bluespec has introduced RISC-V Explorer, a fast, free, and accurate way to evaluate RISC-V cores.
The CHIPS Alliance announced new enhancements to SweRV Core EH2 and SweRV Core EL2.
C-DAC selects Valtrix STING for design verification of RISC-V microprocessors.
Codasip has released three new RISC-V application processor cores that offer multi-core and SIMD capabilities.
De-RISC has developed the first version of its De-RISC MPSoC platform and performance monitoring unit as part of its efforts to create a RISC-V platform for the aerospace market.
Esperanto Technologies has unveiled an accelerator chip for large-scale machine learning applications that uses more than 1,000 RISC-V cores.
Espressif has launched a cost-effective microcontroller with Wi-Fi and Bluetooth LE 5.0 connectivity for secure IoT applications.
GreenWaves Technologies has announced its ultra-low-power GAP9 audio platform, which enables scene-aware active noise cancellation and neural network-based noise cancellation.
Huami releases a new AI chip for biometric wearables.
IAR Systems has collaborated with GigaDevice to provide powerful development tools for GigaDevice's RISC-V based microcontrollers.
IAR Systems and SiFive have enhanced support for the SiFive Insight solution in IAR Embedded Workbench, bringing leading debug and trace capabilities to the RISC-V community.
Imagination Technologies has partnered with RIOS Lab to enable RIOS Lab to build a complete development platform and open source ecosystem for RISC-V single-board computers.
Imperas Software debuts reference models with UVM wrappers for RISC-V verification.
Lynred and GreenWaves Technologies have collaborated to develop a new “Occupancy Management Reference Platform”.
MEEP has developed Coyote, a performance modeling tool designed to provide an execution-driven simulation environment for multi-core RISC-V systems with multi-level memory hierarchies.
Menta and Andes announced a partnership that will allow the reconfiguration of hardware for ISA expansion.
Mentor collaborated with Imperas to conduct RTL coverage-driven design verification analysis for the RISC-V core.
Microchip Technology has announced the launch of a RISC-V-based SoC FPGA development kit to accelerate the deployment and commercial adoption of customer designs across various industries.
Micro Magic, Inc. has introduced a 64-bit RISC-V core that can reach 5GHz and 13,000 CoreMark at 1.1V.
NeuLinker selected Codasip’s Bk5 kernel and Codasip Studio custom toolset for its security and AI-enabled solutions.
OneSpin announced that it will contribute its processor integrity solution to the German government’s ZuSE-Scale4Edge project to ensure the integrity of edge computing processors.
The OpenHW Group implemented the Imperas RISC-V reference model to perform coverage verification on the open source CORE-V processor IP core.
PINE64 has launched a soldering iron that is compatible with Pinecil TS100.
SiFive launches HiFive Unmatched! to make it easy for developers to build a RISC-V PC.
SYSGO and Cobham Gaisler have announced a collaboration to deliver SYSGO’s hypervisor-based real-time operating system, PikeOS, ported to Cobham Gaisler’s IP cores NOEL-V and LEON.
Telink Semiconductor has announced the launch of its TLSR9r SoC family for wireless audio, wearables and other cutting-edge IoT applications.
The European Processor Project has finalized the first version of its RISC-V accelerator architecture, called EPAC.
Think Silicon has introduced a new inference micro-GPU architecture suitable for AI-Vision and graphics tasks.
The University of the Chinese Academy of Sciences (UCAS) has developed NutShell, a 64-bit SoC that operates at up to 200MHz and can run Linux.
zGlue has partnered with Antmicro and Google on the Open Silicon Initiative to create a more open and collaborative ASIC design ecosystem.

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