Bit

name

describe

31:0

BUF1AP

Buffer 1 Address Pointer or TSO Header Address Pointer These bits indicate the physical address of Buffer 1. These bits indicate the TSO Header Address Pointer when the following bits are set :

■ TSE bit of TDES3

■ FD bit of TDES3

Bit

name

describe

31:0

BUF2AP

Buffer 2 or Buffer 1 address pointer . When a descriptor ring structure is used, this bit indicates the physical address of Buffer 2. There is no restriction on buffer address alignment. In 40 or 48 -bit addressing modes, these bits represent the most significant 8 or 16 bits of the Buffer 1 address pointer .

Bit

name

describe

31

IOC

This descriptor generates an interrupt after processing

30

TTSE/TMWD

Transmit timestamp enable or external TSO memory write disable , if TSE bit is not set , this bit enables IEEE1588 timestamping of the transmit packets referenced by the descriptor

If the TSE bit is set and external TSO memory is enabled, setting this bit will disable external TSO memory writes for that packet .

29:16

B2L

Buffer 2 length . The driver sets this field. When set, this field indicates the length of buffer 2 .

15:14

VTIR

VLAN Tag Insertion or Replacement These bits request the MAC to perform VLAN tagging or untagging before transmitting the packet . When VLAN tag insertion, replacement, or removal is enabled for a packet, the application must set the CRC padding control bits appropriately. The following list describes the values ​​of these bits:

■ 2'b00: Do not add VLAN tag.

■ 2'b01: Remove VLAN tags from packets before transmission . This option should only be used for VLAN packets.

■ 2'b10 : Insert a VLAN tag with the tag value programmed in the MAC_VLAN_Incl register or context descriptor.

■ 2'b11 : Replace the VLAN tag in the packet with the tag value programmed in the MAC_VLAN_Incl register or context descriptor . This option should be used only for VLAN packets.

These bits are valid when the Enable SA and VLAN Insertion Tx option is selected when configuring the core.

13:0

HL or B1L

Header Length or Buffer 1 Length For header length, only bits [9:0] are taken . Size 13:0 is only used when interpreting buffer 1 length.

If the TCP Segmentation Offload feature is enabled via the TSE bit of TDES3 , this field is equal to the header length. When the TSE bit is set in TDES3 , the header length includes the length from the Ethernet source address to the end of the TCP header in bytes. The maximum header length supported by the TSO feature is 1023 bytes. The maximum header length supported by the TSO feature is 1023 bytes.

If TCP Segmentation Offload is not enabled , this field is equal to Buffer 1 Length.

Bit

name

describe

31

OWN

After the software prepares the descriptor, it sets this bit to indicate that the DMA owns the descriptor. After the DMA processes the descriptor, it clears this bit, and the software now owns the descriptor.

Note that the software should set this bit last after the descriptor is prepared. This bit is actually the read-write mutex of the hardware and software, and the operation order of the hardware and software is RMW .

30

CTXT

Set to 1 to indicate a Context type descriptor, normally set to 0.

29

FD

Set to 1 to indicate that the buffer data corresponding to this descriptor is the first segment of the MAC frame.

28

LD

Setting it to 1 indicates that the buffer data corresponding to this descriptor is the last segment of the MAC frame. At this time, B1L or B2L cannot be 0.

27:26

CPC

CRC and padding control

This field controls the CRC and padding insertion of the Tx packet . This field is valid only when the first descriptor bit ( TDES3[29] ) FD is set . The following list describes the values ​​of bits [27:26] :

■ 2'b00: CRC and Padding Insertion . The MAC appends a cyclic redundancy check ( CRC ) at the end of transmitted packets whose length is greater than or equal to 60 bytes. The MAC automatically appends padding and CRC to packets whose length is less than 60 bytes.

■ 2'b01: CRC Insertion (Padding Insertion Disabled) The MAC appends a CRC at the end of the transmitted packet but does not append padding. The application should ensure that padding bytes are present in the packets transmitted from the transmit buffer, that is, the packet length of the packets transmitted from the transmit buffer is greater than or equal to 60 bytes.

■ 2'b10 : Disable CRC Insertion The MAC does not append a CRC at the end of the transmitted packet . The application should ensure that the padding and CRC bytes are present in the packet transmitted from the transmit buffer.

■ 2'b11: CRC Replacement MAC replaces the last four bytes of the transmit packet with the recalculated CRC bytes. The application should ensure that the padding and CRC bytes are present in the packet transmitted from the transmit buffer.

This field is valid only for the first descriptor. Note: When the TSE bit is set, the MAC ignores this field because CRC and padding are always inserted for segmentation.

25:23

SAIC

SA source MAC address insertion control

These bits request the MAC to add or replace the source address field in the Ethernet packet with the value given in the MAC Address 0 Register. When SA insertion control is enabled for a packet, the application must set the CRC padding control bits appropriately. Bit 25 specifies the value of the MAC Address register ( 1 or 0 ) to be used to insert or replace the source address . The following list describes the values ​​of bits [24:23] :

■ 2'b0 0 : Does not include the source address

■ 2'b01 : Include or insert source address. For reliable transmission, the application must provide frames without source addresses. ■ 2'b10 : Replace source address. For reliable transmission, the application must provide a source address for the frame.

■ 2'b 11 : Reserved

These bits are valid in EQOS-DMA , EQOS-AXI , and EQOS-AHB configurations when the Enable SA and VLAN Insertion on Tx option is selected when configuring the core and the First Segment control bit ( TDES3 [ 29] ) is set . This field is valid only for the first descriptor.

22:19

SOLTNUM

or THL

SOLTNUM: Slot number control bit in AV mode

These bits indicate the time slot intervals at which data should be taken from the corresponding buffer addressed by TDES0 or TDES1.

When fetching a transfer descriptor, the DMA compares the slot number value in this field with the slot interval held in the RSN field DMA_CH#_slot_Function_Control_Status . Only when the values ​​match, it fetches the data from the buffer. These bits are valid only for AV channels

THL: TCP Header Length If the TSE bit is set, this field contains the length of the TCP header. The minimum value of this field must be 5. This field is valid only for the first descriptor.

18

TSE

TCP Segmentation Enable

When this bit is set, DMA performs TCP segmentation on the packet . This bit is valid only when the FD bit is set.

17:16

CIC/TPL

Checksum Insertion Control or TCP Payload Length These bits control the checksum calculation and insertion. The following list describes the bit encoding:

■2'b00: Checksum insertion disabled.

■ 2'b01: Enable only IP header checksum calculation and insertion. ■ 2'b10 : Enable IP header checksum and payload checksum calculation and insertion, but do not calculate the pseudo-header checksum in hardware.

■ 2'b11: IP header checksum and payload checksum calculation and insertion are enabled, and the pseudo-header checksum is calculated in hardware.

This field is valid when the Enable Transmit TCP/IP Checksum Offload option is selected and the TSE bit is reset. When the TSE bit is set, this field contains the upper bits [17:16] of the TCP payload length . This allows the TCP packet length field to span across TDES3[17:0] to provide support for packet lengths of 256KB . This field is valid only for the first descriptor.

15

TPL

Reserved or TCP Payload Length When the TSE bit is reset, this bit is reserved. When the TSE bit is set, this is bit 15 of the TCP Payload Length [17:0].

This field is valid only if the Enable TCP Segmentation Offloading for TCP/IP Packets option was selected when configuring the core .

14:0

FL/TPL

Packet Length or TCP Payload Length This field is equal to the length of the packet to be transmitted in bytes. When the TSE bit is not set, this field is equal to the total length of the packet to be sent: Ethernet Header Length + TCP /IP Header Length – Preamble Length –

SFD Length + Ethernet Payload Length When the TSE bit is set, this field is equal to the lower 15 bits of the TCP payload length . This length does not include the Ethernet header or TCP/IP header length.

Bit

name

describe

31:0

TTSL

Transmit Packet Timestamp Low The DMA updates this field with the least significant 32 bits of the timestamp captured for the corresponding transmit packet . The DMA writes the timestamp only if the TTSE bit of TDES2 is set in the first descriptor of the packet. This field has a timestamp only if the Last Segment bit ( LS ) in the descriptor is set and the timestamp status ( TTSS ) bit is set.

Bit

name

describe

31:0

TTSH

Transmit Packet Timestamp High The DMA updates this field with the most significant 32 bits of the timestamp captured for the corresponding receive packet . The DMA writes the timestamp only if the TTSE bit of TDES2 is set in the first descriptor of the packet . This field has a timestamp only if the Last Segment bit ( LS ) in the descriptor is set and the timestamp status ( TTSS ) bit is set.

Bit

name

describe

31

OWN

See Read Format

30

CTXT

29

FD

28

LD

27 : 16

reserve

17

TTSS

Tx Timestamp Status This status bit indicates that the timestamp for the corresponding transmit packet has been captured. When this bit is set, TDES2 and TDES3 have the timestamp value captured for the transmit packet. This field is valid only if the last segment control bit ( TDES3[28] ) in the descriptor is set. This bit is valid only if the IEEE1588 timestamp function is enabled; otherwise, it is reserved.

16

reserve

15

ES

Error summary , this bit represents the logical OR of the following bits:

■ TDES3[0]: IP Header Error

■ TDES3[14]: Jabber Timeout

■ TDES3[13]: Packet Flush

■ TDES3[12]: Payload Checksum Error

■ TDES3[11]: Loss of Carrier

■ TDES3[10]: No Carrier

■ TDES3[9]: Late Collision

■ TDES3[8]: Excessive Collision

■ TDES3[3]: Excessive Deferral

■ TDES3[2]: Underflow Error

14

JT

Jabber Timeout This bit indicates that the MAC transmitter has experienced a Jabber timeout. This bit is set only if the JD bit of the MAC_Configuration register is not set.

13

FF

Packet Flush This bit indicates that the DMA or MTL has flushed the packet due to a software flush command given by the CPU .

12

PCE

Payload Checksum Error This bit indicates that the checksum offload engine failed and did not insert any checksum into the encapsulated TCP , UDP , or ICMP payload. This failure could be due to insufficient bytes, as indicated by the Payload Length field of the IP header, or the MTL started forwarding the packet to the MAC transmitter in store and forward mode, but the checksum had not yet been calculated. The second error condition only occurs when the transmit FIFO depth is less than the length of the Ethernet packet being transmitted. To avoid deadlock, the MTL starts forwarding packets when the FIFO is full, even in store and forward mode. This bit is reserved when the full checksum offload engine is not enabled.

11

LOC

Carrier Loss This bit indicates that carrier loss occurred during packet transmission (i.e., the gmii_crs_i signal was inactive for one or more transmit clock cycles during packet transmission). This is valid only for packets sent without collisions and when the MAC is operating in half-duplex mode.

10

NC

No Carrier This bit indicates that the carrier sense signal from the PHY was not asserted during transmission.

9

LC

Late Collision This bit indicates that a packet transmission was aborted due to a collision after the collision window ( 64 bytes including the preamble in MII mode and 512 bytes including the preamble and carrier extension in GMII mode ). This bit has no effect if Underflow Error is set .

8

EC

Excessive Collisions This bit indicates that after 16 consecutive collisions occurred while attempting to transmit the current packet, the transmission was aborted. If the DR bit is set in the MAC_Configuration register , this bit is set after the first collision and the transmission of the packet is aborted.

7:4

CC

Collision Count This 4- bit counter value represents the number of collisions that occurred before a packet was transmitted. When the EC bit is set, the count has no effect.

3

ED

Excess Delay This bit indicates that if the DC bit is set in the MAC_Configuration register , the transmission ended due to excess delay exceeding 24288 bit times ( 155680 bit times in 1000Mbps mode or Jumbo Packet enabled mode ).

2

UF

Underflow Error This bit indicates that the MAC aborted a packet because data arrived late from system memory. An Underflow Error can occur due to any of the following conditions: ■ The DMA encounters an empty transmit buffer while transferring a packet ■ The application fills the MTL Tx FIFO slower than the MAC transfer rate. The transmit process enters the Pause state and the Underflow bit corresponding to the queue in the MTL_Interrupt_Status register is set .

1

DB

Delay Bit This bit indicates that the MAC is delaying before transmitting due to the presence of carrier. This bit is valid only in half-duplex mode.

0

IHE

IP Header Error When IP Header Error is set, this bit indicates that the checksum offload engine detected an IP header error. This bit is only valid when Tx Checksum Offload is enabled. Otherwise, it is left alone. If the COE detects an IP header error, it still inserts the IPv4 header checksum if the Ethernet Type field indicates an IPv4 payload .

Bit

name

describe

31:0

BUF1AP

Header or buffer 1 address pointer .

When the SPH bit of the channel's control register is reset, these bits indicate the physical address of buffer 1. When the SPH bit is set, these bits indicate the physical address of the header buffer to which the Rx DMA writes the L2/L3/L4 header bytes of the received packet . The application can program a byte-aligned address for this buffer, which means that the LS bit of this field can be non-zero. However, at the beginning of transmitting a packet, the DMA performs a write operation with RDES0[1:0] (or RDES0[2:0]/[3:0] in case of 64-/128- bit configuration ) equal to zero. However, the packet data is shifted according to the actual offset given by the buffer address pointer. If the address pointer points to a buffer storing the middle or last part of the packet, the DMA ignores the offset address and writes the complete location indicated by the data width.

Bit

name

describe

31:0

BUF1AP

The upper 32 bits of BUF1AP in 64- bit address mode are not used .

Bit

name

describe

31:0

BUF2AP

Buffer 2 Address Pointer These bits indicate the physical address of Buffer 2. When the SPH bit of the DMA_CH#_Control register is set, the buffer address pointer must be aligned to the bus width, that is, RDES2[3:0 , 2:0 , or 1:0] = 0 , corresponding to 128 , 64 , or 32 bus width. The LSB is ignored internally. When the SPH bit of the DMA_CH#_Control register is reset, there is no restriction on the RDES2 value. However, RxDMA uses the LS bit of the pointer address only when transferring the start byte of a data packet . If BUF2AP gives the address of a buffer that stores the middle or last part of a data packet, DMA ignores BUF2AP[3:0 or 2:0 or 1:0] (corresponding to a 128 or 64 or 32 -bit data bus) and writes the complete location.

Bit

name

describe

31:0

OWN

Same as TX descriptor

30

IOC

Same as TX descriptor

29:26

reserve

25

BUF2V

Buffer 2 Address Valid When this bit is set, it indicates to the DMA that the address of Buffer 2 specified in RDES2 is valid. The application must set this bit so that the DMA can use the address pointed to by the Buffer 2 Address in RDES2 to write received packet data.

twenty four

BUF1V

Buffer 1 Address Valid When set, indicates to the DMA that the address of Buffer 1 specified in RDES1 is valid. The application must set this value if the DMA can use the address pointed to by Buffer 1 Address in RDES1 to write received packet data .

23:0

reserve

Bit

name

describe

31:16

IVT

Inner VLAN Tag If the RS0V bit of RDES3 is set , this field contains the inner VLAN tag of the received packet . This option is valid only if double VLAN tag handling and VLAN tag stripping are enabled .

15:0

OVT

Outer VLAN Tag If the RS0V bit of RDES3 is set , this field contains the outer VLAN tag of the received packet.

Bit

name

describe

31:16

OPC

OAM Sub-Type Code :

When bits [18:16] of RDES3 are set to 3'b111 ;

MAC Control Packet opcode :

When bits [18:16] of RDES3 are set to 3'b110

15

TD

The timestamp of the discard .

This bit indicates that the timestamp for this packet was captured, but it was discarded in the MTL Rx FIFO due to overflow . This bit is available only if the timestamp function is selected. Otherwise, this bit is reserved.

14

TSA

Timestamp Available When a timestamp is present, this bit indicates that the timestamp value is available in the context descriptor word 2 ( RDES2 ) and word 1 ( RDES1 ). This is only valid if the last descriptor bit ( RDES3[28] ) is set. The context descriptor is written in the next descriptor, just after the last normal descriptor of the packet.

13

PV

PTP Version This bit indicates that the received PTP message has the IEEE 1588 Version 2 format. When this bit is reset, it indicates the IEEE 1588 Version 1 format. This bit is available only if you select the Timestamp function. Otherwise, this bit is reserved.

12

PFT

PTP Packet Type This bit indicates that the PTP message is sent directly over Ethernet. This bit is available only if you select the timestamp function. Otherwise, this bit is reserved.

11:8

PMT

PTP Message Type

These bits are available only when the timestamp function is selected.

■ 0000: No PTP message received

■ 0001: SYNC (all clock types)

■ 0010: Follow_Up (all clock types)

■ 0011: Delay_Req (all clock types)

■ 0100: Delay_Resp (all clock types)

■ 0101: Pdelay_Req (in peer-to-peer transparent clock)

■ 0110: Pdelay_Resp (in peer-to-peer transparent clock)

■ 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)

■ 1000: Announce

■ 1001: Management

■ 1010: Signaling

■ 1011–1110: Reserved

■ 1111: PTP packet with Reserved message type

7

IPCE

IP Payload Error When this bit is set, it indicates one of the following: ■ The 16-bit IP payload checksum (that is, TCP, UDP, or ICMP checksum) calculated by the MAC does not match the corresponding checksum field in the received segment . ■ The TCP , UDP, or ICMP segment length does not match the payload length value in the IP header field. ■ The TCP, UDP , or ICMP segment length is less than the minimum segment length allowed for TCP, UDP, and ICMP. This bit is not set when Bit 15 ( ES ) of RDES3 is set

6

IPCB

IP Checksum Bypass This bit indicates that the checksum offload engine is bypassed. This bit is available when you select Enable Receive TCP/IP Checksum Checking.

5

IPV6

IPv6 Header Present This bit indicates that an IPv6 header is detected. When the Enable Split Header Feature option is selected and the SPH bit of the channel control register is set , the IPV6 header is available in the header buffer pointed to by RDES0 .

4

IPV4

IPV4 Header Present This bit indicates that an IPV4 header is detected. When the SPH bit of RDES3 is set, the IPV4 header is available in the header buffer pointed to by RDES0 .

3

IPHE

IP Header Error When this bit is set, it indicates one of the following: ■ The 16 -bit IPv4 header checksum calculated by the MAC does not match the received checksum byte. ■ The IP datagram version and Ethernet type values ​​are inconsistent. ■ The Ethernet packet does not have the expected number of IP header bytes. This bit is valid when Bit 5 or Bit 4 is set. This bit is available when you choose to enable the receive TCP/IP checksum checking feature.

2:0

PT

Payload Type These bits indicate the type of payload encapsulated in the IP datagram processed by the Receive Checksum Offload Engine ( COE ): ■ 3'b0000: Unknown type or unprocessed IP/AV payload ■ March 2001 : UDP ■ March 2010 : TCP ■ March 2011 : ICMP ■ 3'b110 : AV tagged packet ■ 3'b111: AV tagged control packet ■ 3'b101: AV untagged control packet ■ 3'b100: IGMP If IPV4 header is present the bits are set else DCB ( LLDP ) control packet These bits are set to 3'b000 if the COE does not process the payload of the IP datagram due to the presence of an IP header error or a fragmented IP .

Bit

name

describe

31:29

L3L4FM

Number of Layer 3 and Layer 4 Filters Matched These bits indicate the number of Layer 3 and Layer 4 filters that matched the received packet: This field is valid only when Bit 28 or Bit 27 is set high. When multiple filters match, these bits give the number of the lowest filter.

28

L4FM

Layer 4 filter matching

When this bit is set, it indicates that the received packet matches one of the enabled Layer 4 port number fields. This status is given only when one of the following conditions is true:

Layer 3 fields are not enabled, all enabled Layer 4 fields match , all enabled Layer 3 and Layer 4 filter fields match

When more than one filter matches, this bit gives the Layer 4 filter status of the filter indicated by bits [31:29]

27

L3FM

Layer 3 Filter Match When this bit is set, it indicates that the received packet matched one of the enabled Layer 3 IP address fields. This status is given only when one of the following conditions is true: ■ All enabled Layer 3 fields match and all enabled Layer 4 fields are bypassed ■ All enabled filter fields match When multiple filters match, this bit gives the Layer 3 filter status of the filter indicated by bits [31:29] .

26:19

MADRM

MAC Address Match or Hash Value When the HF bit is reset, this field contains the MAC address register number that matches the destination address of the received packet . This field is valid only when the DAF bit is reset. When the HF bit is set, this field contains the hash value of the MAC calculation. When the bit corresponding to the hash value is set in the hash filter register, the packet passes the hash filter.

18

HF

Hash Filter Status When this bit is set, it indicates that the packet has passed the MAC address hash filter. Bits [26:19] represent the hash value.

17

DAF

When this bit is set, the destination address filter fails, which indicates that the packet failed the DA filter on the Mac .

16

SAF

SA Address Filter Failed When this bit is set, it indicates that the packet failed the SA filter in the MAC .

15

OTS

VLAN Filter State When set, this bit indicates that the VLAN tag of the received packet passed the VLAN filter. This bit is valid only when DWC-EQOS-ERVFE is not enabled. If DWC-EQOS-ERVFE is enabled , this bit is redefined to External VLAN Tag Filter State ( OTS ). See “ Filter State ” on page 235 for more information . This bit is valid for both single and double VLAN tagged frames.

14

ITS

Internal VLAN Tag Filter Status ( ITS ) This bit is valid only when DWC_EQOS_ERVFE is enabled. See “ Filter Status ” on page 235 for more details . When dual VLAN processing is enabled, this bit is valid only for double VLAN tagged frames.

13:11

reserve

10

ARPNR

No ARP Reply Generated When this bit is set, it indicates that the MAC did not generate an ARP reply for the received ARP request packet . This bit is set when the MAC is busy sending an ARP reply to an earlier ARP request (it only processes one ARP request at a time). This bit is reserved when the Enable IPv4 ARP Offload option is not selected .

9:0

HL

L3/L4 Header Length This field contains the length of the packet's header as segmented by the MAC at an L3 or L4 header boundary, as recognized by the MAC receiver. This field is valid only if the First Descriptor bit is set ( FD = 1 ).

The header data is written to the buffer 1 address of the corresponding descriptor . If the header length is zero, this field is invalid. This means that the MAC does not recognize and split the header. This field is valid when the " Enable Split Header Function " option is selected.

Bit

name

describe

31

OWN

30

CTXT

29

FD

28

LD

27

RS2V

Receive Status RDES2 Valid When this bit is set, it indicates that the status in RDES2 is valid and is written by DMA . This bit is valid only when the LD bit of RDES3 is set.

26

RS1V

Receive Status RDES1 Valid When this bit is set, it indicates that the status in RDES1 is valid and is written by DMA . This bit is valid only when the LD bit of RDES3 is set.

25

R0V

Receive Status RDES0 Valid When this bit is set, it indicates that the status in RDES0 is valid and is written by DMA . This bit is valid only when the LD bit of RDES3 is set.

twenty four

CE

CRC Error When this bit is set, it indicates that a Cyclic Redundancy Check ( CRC ) error has occurred on the received packet . This field is valid only when the LD bit of RDES3 is set.

twenty three

GP

Jumbo Packet When this bit is set, it indicates that the packet length exceeds the specified maximum Ethernet size of 1518 , 1522 , or 2000 bytes (or 9018 or 9022 bytes if Jumbo Packet Enable is set ). Note: Jumbo Packet indicates only the length of the packet. It does not cause any packet truncation

twenty two

RWT

Receive Watchdog Timeout When this bit is set, it indicates that the receive watchdog timer has expired while receiving the current packet. After the watchdog timeout, the current packet is truncated.

twenty one

OE

Overrun Error When this bit is set, it indicates that the received packet was corrupted due to a buffer overflow in the Rx FIFO . Note: This bit is set only when the DMA transfers a partial packet to the application. This happens only when the Rx FIFO is operating in Threshold mode. In Store-and-Forward mode, all partial packets are completely discarded in the Rx FIFO.

20

RE

Receive Error When this bit is set, it indicates that the gmii_rxer_i signal is asserted during packet reception while the gmii_rxdv_i signal is asserted. This error also includes carrier extension errors in GMII and half-duplex mode. The error can be less extension or no extension or an error during extension ( rxd ! = 0f )

19

DE

Drift Bit Error When this bit is set, it indicates that the received packet has a non-integer multiple of bytes (odd nibbles). This bit is valid only in MII mode.

18:16

LT

Length / Type Field This field indicates whether the received packet is a length packet or a type packet. The encoding of these 3 bits is as follows:

■ 3'b000: The packet is a length packet

■ 3'b001: The packet is a type packet.

■ 3'b011: The packet is an ARP Request packet type

■ 3'b100: The packet is a type packet with VLAN Tag

■ 3'b101: The packet is a type packet with Double VLAN Tag

■ 3'b110: The packet is a MAC Control packet type

■ 3'b111: The packet is an OAM packet type

■ 3'b010: Reserved

15

ES

Error Summary When this bit is set, it represents the logical OR of the following bits:

This field is valid only if the LD bit of RDES3 is set.

■ RDES3[24]: CRC Error

■ RDES3[19]: Dribble Error

■ RDES3[20]: Receive Error

■ RDES3[22]: Watchdog Timeout

■ RDES3[21]: Overflow Error

■ RDES3[23]: Giant Packet

14:0

PL

Packet Length These bits indicate the length in bytes of the received packet that was transferred to system memory (including the CRC ). This field is valid when the LD bit of RDES3 is set and / or the Overrun Error bit is reset. The Packet Length also includes the two bytes appended to the Ethernet packet when IP checksum calculation is enabled and the received packet is not a MAC Control packet. This field is valid when the LD bit of RDES3 is set. When the Last Descriptor and Error Summary bits are not set, this field indicates the cumulative number of bytes that have been transferred for the current packet.