1. Introduction

Earlier we shared the article about writing code to operate IO to confirm the correspondence between IO pins : https://mp.weixin.qq.com/s/biR6j9wt7YxQ2GSXs-UpbQ " Learning FPGA at low cost based on "mining board" " reverse scan all IO pin mappings of the socket.

This method requires knowing the clock pin first, and the operation efficiency is low. In fact, we have a more efficient and direct method, that is, using Jtag boundary scan, which is designed for this type of test requirements.

We need JTAG hardware ( such as Jlink) , host computer tools, and BSDL files. We will introduce the whole process in detail below.

2. Host computer installation

Here we use TopJTAG Probe, which can be downloaded from the official website for trial use , and can be purchased if necessary.

http://www.topjtag.com/probe/

Double-click TopProbe-Setup-1.7.5.exe to start the installation

Click Yes in the pop-up dialog box

Next

Check, Next

Specify the installation path, Next

Install

Finish

Click to evaluate

3. Download BSDL file

https://www.bsdl.info/

Search 325t

Click Download and enter the verification code to download the BSDL file of the specified model.

Xilinx can also be downloaded from the official website

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models.html

4. Operation process

4.1 Create a project

TopJTAG Probe supports different hardware, the most common one is our Jlink emulator, and the one used here is Jlink V9 .

The wiring is as follows

We open the software TopJTAG Probe

Click on the menu bar

File->New Project Wizard

Select Jlink , Next

When the chip is identified , IDCODE will be displayed . Click Next.

Click BSDL File... and select the BSDL file you downloaded earlier.

Continue to click OK

The chip pin diagram will be displayed.

4.2 Monitoring Status

Add observation

Enter the pin name in the following location and press Enter to search

For example, enter T20 here

Right click on T20 and click Add to Qatch and Add to Waveform .

Set up sampling, run

You can see the pin status and waveform. The colors of the pin diagram in the middle represent different states.

4.3 Control Output

Set the sampling mode to execution mode as follows

Added R24 T20 T21 to observations and waveforms

Right-click the pin name Set to 0 to set the pin to output 0 , click Run , and you can see the waveform becomes low

You can see the LED goes off

Set it to 1 again

You can see the waveform is pulled high and the LED is lit

The above demonstrates the input and output operations of the pins, so that the output of any pin can be controlled. By checking which pin corresponds to which pin through an oscilloscope or logic analyzer, you can know the corresponding relationship of the pins on the hardware and complete the reverse IO pin mapping.

5. Conclusion

The above demonstrates how to reverse the mapping relationship of FPAG pins through JTAG . In this way, when you find an FPGA board, you can confirm the pins in the first step, which is convenient for later testing and designing expansion boards.

In fact, we can operate any pin through JTAG , so we can also operate other peripherals connected to the board, such as directly simulating SPI timing by controlling the pin to burn SPI FLSH ( such as TopJTAG Flash Programmer tool ) . We can also develop our own host computer, which can operate any pin. In fact, we can do whatever we want, develop burning tools, test tools, etc., and we can give full play to the development of various interesting and practical tools. For example, when developing embedded file systems, generally when developing test simulations on the PC side, we can only use local file writing to replace FLASH operations. With JTAG, we can directly operate the real SPI FLASH chip, which is a completely real environment.