An engineer who has been working on FPGA for 9 years has a heartfelt opinion
Latest update time：2021-08-31 00:21
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The thing I am most grateful for now is that I have been engaged in FPGA development since I entered the workplace. I feel that experience in FPGA development is very important. It is easy to get started, but it will become more and more difficult to improve. FPGA development is not as simple as writing Verilog and VHDL code. I remember when I first learned Verilog, it took a long time just to figure out which statements can be synthesized and which statements cannot be synthesized. The hardware development language is to be mapped into digital logic circuits. As I work on FPGA for a long time, when writing code, my mind is full of 0/1 flip-flops, and I will gradually map out one by one NAND gates, triggers, memories, and the connections between them, and I will always consider how to design to ensure the smallest area or the lowest delay. After the function is done right, you must also consider the optimization of timing. Even if your function design is perfect and the code is concise, if you don’t consider the timing when designing, everything is just a flower shelf and empty decoration.
A mature FPGA is not just about being familiar with FPGA. The most basic interface protocols can be listed in a lot of them, which is enough for you to study for a long time. If you don’t understand the interface protocols, FPGA is alone. Without data interaction, you can’t do anything. If you want to use FPGA to develop algorithms, you also need to learn more advanced languages for simulation and verification. More importantly, you need to map the algorithm to the hardware resources or peripherals of FPGA, and balance and optimize based on speed, area and function. It is still quite challenging.
FPGA is a unique flower between software and hardware. If you use it for interfaces and communications, it is hardware-oriented; if you use it for algorithms and control, it is software-oriented. Moreover, with the rise of artificial intelligence and machine vision, FPGA is more inclined to the heterogeneity of software algorithms and has the potential to compete with GPUs. Just thinking about it makes me a little excited.
Therefore, my brothers and sisters who are working on or preparing to work on FPGA, we are already on the road. Maybe the road ahead of you is difficult to navigate due to the bumps and bruises, or even a wall blocking the sun, but please believe that the future is bright. Keep going with the spirit of perseverance, and you will gain something every day.
After reading the heartfelt words of this FPGA expert, are you also eager to try it? However, to enter the FPGA field or continue to improve your design level, you still need to plan a learning path that suits you and read the experience summary of those who have come before.
Getting Started with FPGA
For beginners learning FPGA design, it is necessary to start from the basics. Only with a solid foundation can you have the possibility of becoming an expert.
For beginners, there are several steps that must be taken:
Step 1:
Learn about the FPGA structure, what exactly is an FPGA, and what is inside the chip. Don't just start programming with a development board and copying someone else's stuff. Many development board programs are poorly written. I have also worked on development board design for a while, and I think that to a large extent, development boards are misleading. However, the authentic development boards provided by the original manufacturer have excellent codes and can be used as a reference. Only by understanding the internal structure of FPGA can you understand why the overall ideas of writing Verilog and writing C are different.
Step 2:
Master the FPGA design process. Understand what each step is doing and why it is done that way. Aren’t many people just doing those steps? What’s so strange about that? Haha, I think at least half of the people don’t know the difference between synthesize and traslate.
Only by understanding the structure and design process of FPGA can you know how to optimize the design, increase the speed, and reduce resources. Don't be impatient and don't work hard on choosing a language or a company's chip. Language is just a way of expression. What's important is your thinking. Without a good guiding ideology, no matter how well you use the language, you are just a person who understands the language.
Step 3:
Start learning the code. I suggest that anyone who wants to learn the code go to the Altera or Xilinx website to download the code from the original engineers. Don't make mistakes at the beginning.
Step 4:
Template is very important. Whether you can use FPGA resources efficiently depends on understanding the structure of FPGA, understanding the logic functions and basic structures to be realized, and using the correct template. The types of devices inside FPGA are relatively simple. Only by using the template well can your logic be efficiently synthesized into the structure that FPGA is good at expressing:)
To make FPGA, you need to have the idea of circuit. As a beginner, you may not be familiar with the devices, but you should be familiar with the knowledge of digital circuit. FPGA is composed of basic structures such as triggers, lookup tables and interconnects. In fact, what we can see in the code are NAND gates and triggers. Don't equate Verilog with C language. They are completely different things and there is no comparison. When writing a program, you should think about what kind of circuit it is, counters, selectors, tri-state gates, etc., understand timing, and logic is a beat-by-beat thing. In the early stage of design, you should think about it. When the program is not very clear, you can draw a timing diagram, so that the idea will be clearer. In addition, simulation is very important. Don't load it into FPGA after writing the program. You must simulate it first, especially for larger programs. Imagine that you are making ASICs. There is no second chance, so you must do the simulation well. There are still many novices who don't know whether to choose VHDL or Verilog for language learning. Personally, I prefer Verilog. Of course, it doesn't mean that VHDL is not good. Anyway, what is written is circuits, so of course don't spend too much time on the grammar of the language. Verilog is concise and assign always case if else. Mastering these can almost write 90% of the circuits. The above are some of my humble opinions, I hope it will be helpful to everyone.
Five basic skills that FPGA designers need to cultivate
To become a decent FPGA designer, you need to master five basic skills: simulation, synthesis, timing analysis, debugging, and verification.
For FPGA designers, mastering these five basic skills is the same process as using the corresponding EDA tools well. The corresponding relationship is as follows:
1. Simulation: Modelsim, Quartus II (Simulator Tool) riple
2. Comprehensive: Quartus II (Compiler Tool, RTL Viewer, Technology Map Viewer, Chip Planner)
3. Timing: Quartus II (TimeQuest Timing Analyzer, Technology Map Viewer, Chip Planner)
4. Debugging: Quartus II (SignalTap II Logic Analyzer, Virtual JTAG, Assignment Editor)
5. Verification: Modelsim, Quartus II (Test Bench Template Writer)
Although mastering HDL language is not the whole of FPGA design, the impact of HDL language on FPGA design runs through the entire FPGA design process and complements the five basic skills of FPGA design.
For FPGA designers, making good use of the "synthesizable subset of HDL language" can complete 50% of the FPGA design work - design coding.
Practicing the three basic skills of simulation, synthesis, and timing analysis will help you learn the "synthesizable subset of HDL language" in the following ways:
1. Through simulation, the logical behavior of HDL language in FPGA can be observed.
2. Through synthesis, the physical implementation of the HDL language in the FPGA can be observed.
3. Through timing analysis, the physical implementation characteristics of HDL language in FPGA can be analyzed.
For FPGA designers, making good use of the "verification subset of HDL language" can complete the other 50% of FPGA design work - debugging and verification.
1. Build a verification environment to verify the correctness of the FPGA design through simulation.
2. Comprehensive simulation verification can reduce the workload of FPGA hardware debugging.
3. Combine hardware debugging with simulation verification methods, use debugging to solve problems that are not verified by simulation, and use simulation to ensure that problems that have been solved do not reappear during debugging. This can establish a regression verification process that helps maintain FPGA design projects.
These five basic skills of FPGA designers are not isolated, and must be used in combination to complete a complete FPGA design process. Conversely, these five basic skills can be practiced most effectively by completing a complete design process. After you have a preliminary understanding of these five basic skills, you can learn them in depth one by one, and then use the knowledge you have learned again in the complete design process. Repeating this process can gradually improve your design level. With this step-by-step, spiral approach, as long as you get started through training, you can self-study and practice to improve yourself.
In order to ensure the integrity of the structure, the books on FPGA design sold on the market introduce each aspect of FPGA design separately. Although each aspect is in-depth, it is difficult for readers to put it into practice due to the lack of support from other related aspects. Only by reading the whole book can you gain a holistic understanding of FPGA design. Such books are not suitable as engineering training guides, but can be used as reference books for advanced learning in a certain aspect. How to use existing books for self-study is a later story.
For new employees, they often have a preliminary understanding of the overall FPGA design process, and some aspects of the five basic skills may be very solid. However, due to the lack of ability in one or several aspects, their ability to complete the entire design process alone is limited. The purpose of on-the-job training is to help them master the overall design process, cultivate the ability to obtain information by themselves, and form a virtuous cycle of self-promotion and self-development through training back and forth in several design processes. In this process, as the breadth and depth of the knowledge involved in the work gradually become clear, the self-confidence of new employees will gradually increase, and the direction of their personal development will gradually become clear, so that they can actively participate in engineering projects.
Some common questions for beginners
1. Why is it not recommended to learn soft cores such as MicroBlaze?
The performance-price ratio is not high. The performance of a general soft core is about the same as that of Cortex M3 or M4. It is not cost-effective to use something as expensive as FPGA to make a CPU with average performance. It is better to add another M3.
Adding a soft core may affect the functions of other logics. This is when resources are not sufficient. Adding a soft core makes layout and routing quite difficult. The soft core is not open source, so it is not easy to debug when a bug occurs. It is rarely used in engineering and is very likely to be useless.
2. Why is it not recommended to learn ZYNQ or SOC from scratch?
You should learn as simple things as possible when you are getting started, either focusing on ARM or FPGA. This will make it easier to feel a sense of accomplishment and increase your confidence.
The application fields of ZYNQ and SOC are not wide, and many people have never heard of this kind of thing, which makes it difficult to find a job. The development tools take a long time to compile, which wastes a lot of time. In most jobs, you are only responsible for one aspect, which means that the other aspect may not be useful.
3. Why do we still need to write HDL when there are so many IP cores?
Those who ask this kind of question are usually students. They have never made a product and have never encountered engineering problems. IP cores are not omnipotent and cannot meet all needs. Try to use closed-source IP cores as little as possible. Once a problem occurs, this black box may make the product difficult to produce.
A deeper understanding of the lower level allows for better use of the higher level. This rule applies to all programming languages.
I have been doing FPGA development for more than 9 years now, and I am considered an older engineer. During this period, I have been involved in some work such as project management and technical support. I don’t know why, I always feel uneasy when I am separated from R&D to do these jobs. Maybe I am born to be good at technology. I just don’t know what will happen if I continue to work so hard. I used to be very confused, fearing that as I get older, my energy will not be as good as that of young people, and I will be gradually eliminated because I will not be able to work overtime and stay up late. I won’t go into details about the confusion. Fortunately, I have thought a lot and gradually figured out a lot. I hope that you who read this article can stick to it like me, don’t be afraid when encountering problems, have the spirit of working hard to the end, accumulate slowly, understand slowly, and make a name for yourself in the FPGA circle.
Source:
Internet compilation.
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