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Reading for rewards | Read chip design books and participate in Mentor's rewarded knowledge test

Latest update time:2018-03-19
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I remember that some engineers seem to have plans to read more serious books in 2018. If you haven't started yet, you might as well start here. If you don't have a reading plan, it's always a good idea to read more books .



✎From now until March 31

Read Mentor's "Mentor Catapult Tool Case Study: Low Power Design is the Core Value of ARM" or "Physical IP Exemption Management Using CALIBRE AUTO-WAIVERS". Click to read the original text and pass any of Mentor's prize-winning tests to have a chance to participate in the lucky draw.

Book 1: Mentor Catapult Tool Case Study: Low-power design is the core value of ARM



Since its inception, ARM® has been committed to providing scalable, low-power, high-performance IP. The ARM architecture is the standard for low-power mobile applications, automotive/embedded solutions and Internet of Things (IoT) designs. Most customers who adopt ARM IP are interested in the low-power architecture of their products. Therefore, low power consumption is a core value of ARM, and every team member explores power saving opportunities at every design level. From the application to the transistor level, ARM can support low-power design with a systematic approach (Figure 1).


Every element of a system may generate power consumption, but this article focuses on RTL IP design with high power efficiency, including: setting low power consumption goals, understanding low power consumption design flow, and optimization techniques.

Book 2: Physical IP Exemption Management Using CALIBRE AUTO-WAIVERS




To develop physical IP for chip integration, library and module designers need to be able to identify approved waivers in their data to avoid unnecessary three-way conversations between IP providers, chip integrators, and foundries to review acceptable waivers. The Calibre® Auto-Waivers™ solution provides a repeatable, standardized process for waivers of IP results, streamlining communication and shortening lengthy debug cycles for design implementation teams.

Click to read the original text to participate in the event and start learning from the core~


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