UMC cooperates with Cadence to provide 28nm design reference flow, suitable for ARM Cortex-A7 MPCore-based system-on-chip

Highlights:

· The design flow includes CadenceEncounter digital design implementation system, Tempus timing signoff solution, Voltus IC power integrity solution, Quantus QRC parasitic parameter extraction solution, physical verification system, Litho physical analyzer and CMP predictor.

· UMC UMC achieves 1.7GHz ARM Cortex-A7 performance and power consumption indicators and less than 200mW dynamic power consumption

^{San Jose, California ,} USA, January 20, 2015 – Cadence (NASDAQ: CDNS), a global leader in electronic design innovation, today announced that United Microelectronics Corporation (NYSE: UMC; TWSE: 2303), the world’s leading semiconductor foundry, has adopted Cadence® designs Implementation and signoff tools for the production of silicon-ready 28nm ARM® ^Cortex® - ^A7 , MPCore-based SoCs targeting entry-level smartphones, tablets, high-end wearables and other advanced mobile devices. Compared with the previous generation solution, the use of the Cadence solution enabled UMC to shorten the tape-out time by 33% and achieve 1.7GHz performance; in addition, UMC also achieved a dynamic power consumption of less than 200mW, which is better than the previous generation. The design process was reduced by 20%.

^{Adopts Encounter®} digital design implementation system based on multi-threading technology , including GigaOpt route-driven optimization and CCOpt concurrent clock data path optimization, thereby achieving faster turnaround time and gaining performance, chip area and Significant increase in drive power consumption. In addition, the seamless integration of Tempus™ timing signoff solution, Voltus™ IC power integrity solution, Quantus™ QRC parasitic parameter extraction solution, physical verification system, Litho physical analyzer and CMP predictor enables UMC to Perform signoff checks earlier in the process to ensure that the design functions as expected.

“Cadence’s massively parallel architecture allows us to significantly reduce the time spent on signoff analysis, design implementation and convergence, so we can quickly deliver high-quality reference designs to the market that are better than any other in terms of power consumption, performance and area. Regarding expected indicators, Lin Shiqin, senior director of IP development and design support department of UMC, said: "Our mobile product customers have very special equipment needs. The test chip based on this process has passed the chip test, ensuring that customers receive reliable 28nm Silicon -ready reference design. "