What are the lectures next week? Detailed explanation of system analysis, PCB design and packaging special sessions
high speed? 3.5Gbps? 10Gbps? 100Gbps?
Yesterday's high-speed challenge is now a common design.
Of course, you can figure out signal reflections, signal insertion loss, and signal crosstalk with paper and pen; you can use traditional methods for physical design. But for real engineering implementation, no one has so much time!
Instead, Cadence's Allegro, Sigrity, Clarity tools can help you!
Cadence sincerely invites you to attend the "2019 Cadence China Technology Seminar".
For system analysis, PCB design and packaging, we will have two topics to introduce to you the latest research and development progress of the latest tools! The one-day seminar will share with you Cadence's latest R&D results and progress in high-speed PCB design, system-level packaging, and Die-to-Die system simulation, and demonstrate Cadence's unique IC/Package/Broad collaborative design to electronic design engineers. and system-level analysis solutions.
Conference registration
Please click on the following QR code to complete online registration:
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System Analysis |
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09:00 - 09:30 |
Registration |
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09:30 - 10:20 |
What's New in Sigrity |
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10:20-11:10 |
True 3D Analysis of Large Geometries with Clarity 3D Solver |
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11:10-12:00 |
System PDN Design and Optimization with Package Model |
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12:00-13:00 |
Lunch |
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13:00-14:00 |
Electrical/Thermal Co-Simulation Technology |
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14:00 - 14:40 |
Simulating GDDR6 and 112G-PAM4 with Sigrity SI technology |
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14:40 - 15:20 |
Thermal aware DC analysis for multi-level tree topology |
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15:20 - 15:50 |
Wrap-Up and Lucky Draw |
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PCB and Package |
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09:00 - 09:30 |
Registration |
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09:30 - 10:20 |
Accelerating Product Development |
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10:20-11:00 |
Actionable Analysis Results – Avoiding the Back and Forth with PCB Designers |
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11:00-11:50 |
Enable Heterogeneous Integration Integrated Design With Cadence 2.5d/3D -IC Flow |
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11:50-13:00 |
Buffet Lunch |
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13:00-14:00 |
Data-driven PCB Design from Extended Enterprise to the Engineers Desktop |
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14:00 - 14:40 |
Rules-Based Footprint and 3D Model Generation |
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14:40 - 15:30 |
Applying team design and DFM checking to IC Package and Sip |
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15:30-16:00 |
Wrap-Up and Lucky Draw |
Xi'an Railway Station
Time: June 11, 2019 (Tuesday)
Location: Shangri-La Hotel, Xi'an, 2nd floor
Chengdu Station
Time: June 13, 2019 (Thursday)
Location: Chengdu’s first Renaissance Hotel, 3rd floor
Shanghai Station
Time: June 17, 2019 (Monday)
Location: Evergreen Laurel Hotel Pudong, Shanghai, 2nd floor
Shenzhen Station
Time: June 19, 2019 (Wednesday)
Location: The Westin Hotel Shenzhen Yitian, 4th floor
Beijing Station
Time: June 21, 2019 (Friday)
Location: Beijing Liting Huayuan Hotel, 3rd floor
Thanks to the following special sponsors
Xi'an Railway Station
Shanghai Station
Shenzhen Station
Beijing Station
Chengdu Station
About Cadence
Cadence Corporation is committed to enabling electronic systems and semiconductor companies to design innovative end products that change the way people work, live and play. Customers use Cadence's software, hardware, IP and services, covering everything from semiconductor chips to circuit board design and even entire systems, to help them deliver products to the market faster. Cadence's innovative "Intelligent System Design" strategy will help customers develop more differentiated products, whether in mobile devices, consumer electronics, cloud computing data centers, automotive electronics, aviation, the Internet of Things, Industrial applications and other application markets. Cadence was also selected as one of the "100 Best Companies to Work for in the World" by Fortune magazine. To learn more, please visit the company's website at www.cadence.com.
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