Cadence launches new Neo NPU IP and NeuroWeave SDK for silicon design to accelerate device-side and edge AI performance and efficiency

Latest update time：2023-12-20 17:28

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Executive summary

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Neo NPU efficiently handles load from any host processor, scaling from 8 GOPS to 80 TOPS on a single core and hundreds of TOPS on multiple cores

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AI IP delivers industry-leading AI performance and energy efficiency, enabling optimal PPA results and price/performance

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Targeting a wide range of on-device and edge applications, including smart sensors, IoT, audio/visual, hearable/wearable devices, mobile vision/voice AI, AR/VR and ADAS

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Comprehensive, versatile NeuroWeave SDK addresses the needs of all target markets with a broad range of Cadence AI and Tensilica IP solutions

Shanghai, China, September 20, 2023 - Cadence Electronics (Cadence, Inc., NASDAQ: CDNS) recently announced the launch of a new generation of AI IP and software tools to meet the growing market demand for device-side and edge AI processing. The newly launched Cadence ^® Neo ^™ Neural Processing Units (NPU) have strong scalability and can provide a wide range of AI functions for low-power applications, raising the efficiency and performance of AI SoC to a new level. Neo NPU single-core configuration delivers performance up to 80 TOPS, supports classic AI models and the latest generative AI models, and is equipped with easy-to-use scalable AMBA ^® AXI interconnect to handle AI/ML workloads from any processor, including applications Processors, general-purpose microprocessors and DSPs. NeuroWeave ^™ Software Development Kit (SDK) complements AI hardware and provides developers with a one-stop AI software solution covering Cadence AI and Tensilica ^® IP products to achieve "zero-code" AI development.

“The recent focus on AI has been on the cloud, but the applications of traditional AI and generative AI at the edge and on the device are also very promising,” said Bob O’Donnell, president and principal analyst at TECHnalysis Research . “From consumer electronics to mobile phones and From cars to enterprises, we are ushering in an era of convenient smart devices. To achieve these goals, chip designers and device manufacturers need flexible and scalable joint software and hardware solutions for varying power consumption and computing performance needs. It’s important that new chip architectures are optimized to accelerate machine learning models and software tools and integrate seamlessly with popular AI development frameworks while delivering AI capabilities to applications. The essential."

The flexible Neo NPU is ideally suited for power-sensitive devices and high-performance systems with configurable architecture, enabling SoC architects to design solutions for smart sensors, IoT and mobile devices, cameras, hearables/wearables, PCs, The best artificial intelligence inference solutions are integrated into various products such as AR/VR headsets and advanced driver assistance systems (ADAS). New hardware and performance enhancements and key features/capabilities include:

Scalability

Single-core solution scales from 8 GOPS to 80 TOPS, multi-core further scales to hundreds of TOPS

Wide range of configurations

Supports 256 to 32K MACs per cycle, allowing SoC architects to optimize their embedded AI solutions to meet power, performance, and area (PPA) tradeoffs

Integrated support for various network topologies and carriers

Efficiently run inference tasks from any host processor, including DSPs, general-purpose microcontrollers, or application processors, significantly improving system performance and reducing power consumption

Easy to deploy

Accelerate time to market to meet the ever-changing needs of next-generation vision, audio, radar, natural language processing (NLP) and generative AI pipelines

flexibility

Supports Int4, Int8, Int16 and FP16 data types, covering a variety of operations that form the basis of CNN, RNN and Transformer-based networks, providing flexibility to trade off the performance and accuracy of neural networks

High performance and efficiency

Compared with the first generation Cadence AI IP, performance can be improved by up to 20 times, inferences per second per area ( IPS/mm2 ) increased by 2-5 times, and inferences per second per watt ( IPS/W ) increased by 5-10 times

Software is a key component of any AI solution, so Cadence has also upgraded its general software tool chain and launched NeuroWeave SDK. NeuroWeave SDK provides customers with a unified, scalable, and configurable software stack across Tensilica DSPs, controllers, and Neo NPUs to meet the needs of all target applications, simplify product development, and easily migrate as design requirements change. NeuroWeave SDK supports many industry-standard domain-specific machine learning frameworks, including TensorFlow, ONNX, PyTorch, Caffe2, TensorFlow Lite, MXNet, JAX, etc. for automated end-to-end code generation; Android neural network compiler; TF Lite Delegates; and TensorFlow Lite Micro for microcontroller-class devices.

"For two decades and more than 60 billion processors shipped, industry-leading SoC customers have relied on Cadence processor IP to design cutting-edge on-device SoCs. Our Neo NPU builds on this expertise to enable AI "Leaps in processing power and performance," said David Glasco, vice president of research and development for Cadence Tensilica IP . "Today's rapidly changing market landscape requires us to ensure that customers can design outstanding AI solutions based on unique requirements and KPIs without worrying about the nerves down the road. Network support issues. In order to achieve this, we have invested a lot of manpower and material resources to develop new AI hardware platforms and software tool chains, continuously optimizing in terms of performance, power consumption and cost, and promoting the rapid deployment of AI systems.”

“Labforge used a set of Cadence Tensilica DSPs when developing the Bottlenose smart camera product line to deliver best-in-class AI processing performance for power-sensitive edge applications,” said Yassir Rizwan, CEO of Labforge, Inc. “Cadence’s AI software is An integral part of our embedded low-power artificial intelligence solutions, we look forward to Cadence's new NeuroWeave SDK delivering new capabilities and improved performance with an end-to-end compiler toolchain flow. To better solve the AI challenges in the field of automation and robotics - speed up product launch, make full use of application needs based on generative AI, and open up new markets that cannot be achieved through other means."

Neo NPU and NeuroWeave SDK support Cadence's Intelligent System Design ^™ strategy, which aims to achieve ubiquitous intelligence through superior SoC design.

Availability

Neo NPU and NeuroWeave SDK are expected to be generally available in December 2023. An early participation program for key customers has begun.

To learn more, please visit

www.cadence.com/go/NPU

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About Cadence

Cadence is a key leader in electronic systems design with more than 30 years of expertise in computing software. Based on the company's intelligent system design strategy, Cadence is committed to providing software, hardware and IP products to help electronic design concepts become reality. Cadence's customers are the most innovative companies around the world, delivering chips and circuit boards to the most dynamic application markets such as hyperscale computing, 5G communications, automotive, mobile devices, aerospace, consumer electronics, industrial and medical. to complete systems of superior electronics. Cadence has been ranked among Fortune magazine's 100 Best Companies to Work For for nine consecutive years. For more information, please visit the company's website at www.cadence.com.

© 2023 Cadence Design Systems, Inc. All rights reserved. All rights reserved worldwide. Cadence, the Cadence logo and other Cadence marks listed at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other marks are the property of their respective owners.

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