The Care and Feeding of FPGA Power Supplies

Modern FPGAs are among the most complex integrated circuits ever created, using the most advanced transistor technology and cutting-edge architecture to achieve incredible flexibility and maximum performance. As time passes and technology advances, this complexity dictates that certain compromises need to be made when designing and implementing systems with FPGAs. This is most evident in power supplies, which have to improve accuracy, flexibility, controllability, efficiency, and fault awareness with each FPGA generation, while also reducing size.

Engineers should spend most of their time programming—they don’t want to spend time and energy thinking about how to design a suitable power supply. In fact, the best power supply solution is to adopt a powerful, flexible and effective design that can meet the current needs of the project and meet the needs of project upgrades and development. Here, we will take a closer look at some important power supply specifications and what they mean.

Core supply voltage is one of the most important keys to balancing FPGA power consumption and performance. Specification documents give a range of acceptable voltages, but the total voltage range is not the whole story. As with everything, trade-offs and optimizations need to be made.

Table 1 is an example of the core voltage specifications for the popular Altera Arria 10 FPGA. While these numbers are specific to the Arria 10, they are representative of other FPGA core voltage requirements. The voltage range is the nominal voltage plus a tolerance of ±3.3%. Within this voltage window, the FPGA will operate normally, but the full picture is much more complex.

Table 1. Altera Arria 10 Core Voltage Specifications

Note the row labeled “SmartVID”, which has a voltage range of 0.82 V to 0.93 V. This represents the various voltages that the FPGA can accept when the FPGA requests its own core voltage through the SmartVID2 interface (described later). This SmartVID specification states a fundamental fact about FPGAs: FPGAs can operate at different voltages, depending on their specific manufacturing tolerances and the specific logic design used. The quiescent voltage of FPGAs can vary. The power supply must be able to respond and adapt.

设计目标是产生恰好能满足编程功能需求的性能水平，不消耗不必要的功率。根据半导体的物理特性以及 Altera、Xilinx ^® （图1）和 其他公司公布的数据可知，动态和静态功率会随着内核 V _DD 的增加而显著提高，因此我们的目标是确保，给 FPGA 提供的电压刚好达到其时序要求即可。功耗过大无助于提高性能。实际上，功耗过多会使情况变得更糟，因为晶体管泄漏电流随着温度的升高而增加，从而消耗更多不必要的功率。由于这些原因，当务之急是优 化设计和工作点的电压。

Figure 1. Xilinx Virtex V power vs. core V _CC .

This optimization process requires very accurate power supplies to be successful. Regulator errors must be factored into the error budget and subtracted from the available voltage range for optimization. If the core voltage drops below the required voltage, the FPGA may fail due to timing errors. If the core voltage drifts above the maximum specification, the result may be damage to the FPGA, or hold time failures may form in the logic. To prevent all of these situations, the power supply tolerance range must be considered and the command voltage must be kept within the specification limits.

The problem is that most power regulators are not accurate enough. The regulated voltage could be anywhere within the tolerance of the commanded voltage, which can drift with load conditions, temperature, and aging. A power supply that guarantees a ±2% tolerance can regulate the voltage anywhere within a 4% voltage window. To compensate for the voltage potentially being 2% below the lower limit, the commanded voltage must be increased to 2% above the timing requirement. If the regulator then drifts 2% above the commanded voltage, it will operate at 4% above the minimum voltage required for that operating point. This still meets the specified voltage requirement of the FPGA, but wastes a lot of power (Figure 2).

Figure 2. Power regulator tolerance trade-offs.

The solution is to choose a power regulator that supports tighter voltage tolerances. A regulator with a tolerance of ±0.5% can operate closer to the minimum specification at the required operating frequency and guarantee a deviation of less than 1% from the required voltage. In this case, the FPGA will operate normally and its power consumption will be the lowest level under this operating condition.

The LTC388x series power supply controller can guarantee a regulated output voltage tolerance better than ±0.5% over a wide configurable voltage range. The LTC297x series power system manager can guarantee an adjusted voltage regulator tolerance better than ±0.25%. Under these precision conditions, it is clear that for FPGAs, the best balance between power consumption and performance can be achieved.

A more subtle implication of power supply accuracy is in the thermal budget. Since static power consumption is far from negligible, FPGAs heat up even when doing nothing. Increased temperature results in more static power consumption, which further increases operating temperature (Figure 3). Adding unnecessary voltage to the power supply only makes the problem worse. An inaccurate power supply requires a working voltage protection stage to ensure that there is enough voltage to do the job. Supply voltage uncertainties caused by tolerances, system component variations, and changes in operating temperature can produce voltages significantly higher than the required minimum. When applied to the FPGA, this extra voltage can cause thermal effects and can even lead to thermal runaway under high processing loads.

Figure 3. Supply current vs. operating temperature.

The remedy is to choose a very accurate power supply that produces only the right voltage and no more than necessary, which is exactly what ADI power system management (PSM) devices excel at.

SmartVID is a technology from Altera that is used to provide the optimal voltage for each FPGA, as required by the FPGA itself. There is a register inside the FPGA that contains a device-specific voltage (programmed at the factory) that ensures efficient operation of the FPGA. An IP function compiled inside the FPGA can read this register and send a request to the power supply through an external bus to provide this precise voltage (Figure 4). Once the voltage requirement is reached, it will remain static during operation.

Figure 4. Altera SmartVID structure.

The power requirements of SmartVID applications include specific bus protocols, voltage accuracy, and speed. The bus protocol is one of several methods that the FPGA uses to communicate its required voltage to the power regulator. Of the available methods, PMBus is the most flexible because it can meet the needs of the widest range of power management ICs. The SmartVID IP uses two PMBus commands: VOUT_MODE and VOUT_COMMAND, which are used to command PMBus-compliant power regulators to the correct voltage.

The voltage accuracy and speed requirements for the regulator include autonomously booting the voltage (before PMBus activation), being able to accept a new voltage command every 10 ms, being able to step 10 mV every 10 ms during the voltage regulation phase, and being able to settle to within 30 mV (~3%) of the target voltage within a 10 ms step time, finally ramping up to the commanded voltage and remaining stationary during FPGA operation.

Although Altera uses SmartVID technology, there are other similar technologies used in the industry that can accomplish the same task. One of the simplest methods is to test each board at the factory and program a precise voltage in the non-volatile memory of the power supply to optimize the performance of that specific board. When using this technology, no further intervention is required for the power supply to operate at the correct voltage. This is one of the advantages of a power supply manager or controller with EEPROM.

The LTC388x family of power supply controllers meets all of Altera's SmartVID requirements. In addition, the LTM4675/LTM4676/LTM4677 µModule regulators easily meet these requirements and provide a complete solution in a single compact form factor.

The computing speed of any logic block depends on its supply voltage. Within limits, the higher the voltage, the faster the performance. We have seen why we cannot simply run at the highest voltage to guarantee the best speed. On the other hand, we must make the operating voltage high enough to meet the application requirements, as shown in Figure 5.

Figure 5. The trade-off between FPGA operating frequency and VDD.

An important lesson from Figure 5 is what can be done when a particular design fails its logic timing requirements and is in the failure zone. Often, before a design is converted to hardware, it is difficult to accurately define the boundary between normal operation and failure, and it is impossible to determine in advance at which specific voltage it will exceed timing requirements. The only options are to determine a voltage well above the minimum in advance, wasting power to ensure functionality, or to design a flexible power supply that can adapt to the hardware needs during test or, in the case of SmartVID technology, even at power-up. The ability to adapt to unknown needs makes the accuracy of ADI PSM devices even more valuable, because FPGA designers can make trade-offs between power and performance during the actual design phase and at any stage of development.

*This article is excerpted from the technical article "Care and Feeding FPGA Power Supplies: The How and Why of Success" in ADI's Analog Dialogue magazine. The full article can be viewed on the ADI website. In addition, you can also apply for a free print version of Analog Dialogue to read more of ADI's popular articles. If you need it, please click "Read the original article" to apply.