collect! Design guidance for a high-performance converter

That's the beauty of reusability, but in real life everything doesn't work out. The main disadvantage of using a single device for multiple applications is that you give up the customization and optimization needed to achieve the absolute highest possible performance for DC, seismic, audio and higher bandwidth applications. In the rush to reuse and complete a design, precise performance is often sacrificed. One major aspect of it that is easily overlooked and ignored is the clock. In this article, we discuss the importance of clocking and provide guidance on the proper design of high-performance converters.

Relationship between Jitter and Signal-to-Noise Ratio

When reviewing the existing literature, we saw numerous descriptions of the dependence of ADC performance on jitter parameters, and often such titles would include the word "high speed," which makes sense. In order to examine the relationship between jitter and signal-to-noise ratio (SNR), first look at the relationship between SNR values ​​and rms jitter.

If jitter is the dominant noise source in the system, this relationship simplifies to:

If you have different noise sources, you need to use Equation 2 to calculate the combined SNR:

in:

e _v is the simplified voltage noise rms

δt _RMS is the total rms jitter estimated as the sum of rms from various sources:

The summation is valid for uncorrelated noise sources. Using Equation 2, the SNR based on thermal noise (e2v) and jitter noise is obtained. The effect of jitter on SNR depends on the input frequency (f _IN ). This means that at higher frequencies, SNR is primarily defined by jitter. Figure 1 shows the jitter-affected curves for ideal and real ADCs based on Equation 1 and Equation 2. The curves in Figure 1 are common in high-speed ADC data sheets, but usually start in the MHz range. For precision ADCs, we will further demonstrate the same dependence in the kHz range. We achieved an SNR of over 108dB (see Figure 1), which precision ADCs are now able to do. This is where the AD7768-1 comes in.

Figure 1. Relationship between SNR and fIN at different jitter levels.

Looking at the curves in Figure 1, we can see that the AD7768-1 converting a 1kHz signal (gray line) is affected by clock jitter only when σt _RMS exceeds 300ps. We can adjust the variables and display the jitter requirements for a specific ENOB and _{fIN :}

Figure 2. The relationship between the maximum allowable jitter and fIN under different ENOB of the converter.

The current target jitter of high-precision converters leaves designers with no option to use a general-purpose oscillator (such as the 555 timer oscillator) or many microcontroller or FPGA-based clock generators. We can only choose crystal (XTAL) and phase locked loop (PLL) oscillators. New MEMS oscillator technologies will also be suitable.

Does oversampling technique work here?

An important point can be observed in Equations 1 and 2, that jitter has no obvious dependence on the sampling frequency. This means that it is difficult to reduce the effects of jitter through oversampling techniques (planar or noise shaping). Oversampling is common in high-precision systems but does little to combat jitter noise. The relationship with sampling frequency is shown in Equation 4

Generally speaking, increasing f _S is of little use in improving jitter. Theoretically, the ADC's oversampling rate will reduce some of the wideband jitter effects. 3In terms of quantization noise and thermal noise, noise shaping is a very effective method to suppress noise in the target frequency band. As shown in Equation 7, increasing the oversampling rate rejects quantization noise faster than noise jitter suppression (Equation 5). This makes jitter more prominent in oversampled structures that utilize noise shaping. In a Nyquist converter, this may not be as serious. Figure 3 illustrates this phenomenon using the second-order Σ-ΔADC and the new fourth-order Σ-ΔADC as examples.

Figure 3. Oversampling reduces quantization noise below the noise limit due to dithering.

Point A shows that a fourth-order Σ-Δ ADC requires clock jitter below 30 ps.

Point B illustrates that 200 kHz conversion using older technology second-order shapers is not affected by jitter levels as high as 200 ps.

The relationship between the quantization noise shaped at an oversampling rate M using an N-order shaper with a basic error of Δ:

The relationship between the oversampling rate M and the amount of jitter:

Equation 7 shows second-order noise shaping (N = 2). Attention should be focused on M, which now changes to the power of 5.

Different generations of converters will see some common relationship characteristics. First-order noise shapers hide jitter the longest, thus pushing the cubic relationship to ~1/M ³ , while fourth-order Σ-Δ will obtain a ~1/M ⁹ relationship. Jitter will be reduced by at most 1/M, which usually assumes the presence of a strong broadband frequency component rather than the relationship 1/(f ^N ).

Does signal amplitude change the status quo?

Equation 2 shows that there is amplitude in both the numerator and the denominator, preventing a good balance between amplitude and SNR values. In an attenuated signal, in addition to jitter, thermal noise begins to limit the dynamic range, thus worsening the SNR. Therefore, we can see that if low enough noise is achieved with the new precision ADC, the precision ADC will be jitter limited in almost all applications (except dc/seismic applications).

Clock jitter will also have a spectrum

In the previous introduction, we established the relationship between signal, total voltage noise, and clock jitter rms. SNR ties these three together through the very simple equation 2. SNR is a good benchmark for comparing circuit designs, but may not be feasible in practical applications. In many applications, designing specifically for SNR is less than ideal. Therefore, spurious-free dynamic range (SFDR) becomes the design goal. In new high-precision systems, 140dB or even 150dB SFDR can be achieved.

The process of signal distortion caused by the clock source can be examined by mixing the two. FM modulation theory can be used to analyze the frequency domain. The resulting fast Fourier transform (FFT) spectrum is a mixture of the clock source spectrum and the input signal spectrum. To see how our ADC is affected by this, we introduce phase noise. Both jitter and phase noise describe the same phenomenon, but one will be preferred based on the application. We have shown how to convert phase noise into jitter in Equation 3. During the integration process, the nuances of the spectrum are lost.

Phase noise density plots are often provided with clock source device and PLL specifications. The curves shown in Figure 4 become less common for lower frequency sources, which are used in current oversampling converters but report total jitter values ​​(rms or peak).

Figure 4. Phase noise density plot of the AD9573 100 MHz/33.33MHz clock generator .

By chopping the resistor and transistor elements can be forced to exhibit fairly flat noise characteristics near DC. No equivalent clock chopper circuit is available.

When converting a high-amplitude AIN signal, the resulting FFT becomes an FM modulated spectrum, where the AIN acts as the carrier and the clock sidebands are equivalent to the signal. Note that phase noise is not band limited in the FFT, the noise appears as multiple image aliasing segments within the band (see Figure 5).

Figure 5. Near-carrier phase noise determines the amplitude of the FFT band around the main frequency band.

In precision ADCs, it is often possible to rely on the natural attenuation characteristics of phase noise without providing any clock anti-aliasing filters. Some jitter can be reduced by adding filtering to the clock source—for example, using a tuning transformer in the clock path to exhibit the desired frequency response. Finding the upper limit of the integration frequency (Equation 3) is not easy to determine. Precision ADC data sheets don't offer much advice on this. In these cases, engineering assumptions are made about the clock CMOS input.

A more common problem in precision ADCs occurs near the f _IN frequency, where phase noise in the shape of 1/(f ^N ) will make the SFDR characteristics worse. The large A _IN signal will act as a blocker, a term more commonly used in radio receivers that applies here as well.

When aiming to record high-precision spectra with very long acquisition times, the timing will be greatly affected due to the nature of the clock phase noise spectral density. SNR and FFT plots can be improved by shortening the acquisition time (wider frequency band). For a given FFT capture, the rms jitter should be calculated as the integrated phase noise of the frequency band. Looking at Figure 5, this can be clearly seen.

While this technique can significantly improve the FFT and SNR curves, it does not help in observing the signal near the blocker. An important generalization and simplification of the FM modulation equation is that edge height is proportional to:

Extending the integration time of a single FFT is a challenge and requires further capturing more and more prominent parts of the phase noise. We need to consider alternative ways of combining longer captures to improve this.

Figure 6. Phase noise aliases down to baseband.

For practical considerations, the SSB curves should be compared at a single point at f _BIN /2 offset frequency to select a better source and obtain a clean near-carrier spectrum and SFDR. If you compare sources to achieve better SNR, you need to perform the integration in Equation 3 from f _{BIN /2 to over 3 times fS (jitter alias).}

The previous description applies to any ADC regardless of architecture and technology . Challenges posed by specific technologies are discussed below. One of the most prominent examples of jitter dependence is the sigma-delta ADC. The difference between discrete-time and continuous-time modulators makes a big difference in terms of jitter immunity.

Continuous-time and discrete-time sigma-delta ADCs are not only affected by jitter associated with sampling, but their feedback loops can also be severely disturbed by jitter. The linearity of the DAC elements in discrete-time and continuous-time modulators is key to achieving high performance. The importance of a DAC can be intuitively understood by connecting it in parallel with an operational amplifier (opamp). If designing a voltage amplifier with a gain equal to 2, the circuit designer usually first considers using an op amp and two resistors. If the external environment is not extreme, the circuit shown in Figure 7a will meet the requirements. In most cases, circuit designers do not need to understand op amps to achieve good performance. The designer must choose resistors that are well matched and precise enough to obtain the correct gain. To reduce noise, the resistor must be small. Thermal coefficient matching needs to be considered in terms of thermal performance.

Figure 7. Op amp compared to sigma-delta ADC.

Note that none of these dependencies are determined by the op amp. For this circuit operation, the effects of op amp imperfections are not important. Yes, input current or capacitive load can have a big impact. The slew capability needs to be checked because if the bandwidth is not limited, noise effects may be a concern. But these problems can only be solved if the correct resistor is selected without affecting performance. In sigma-delta AC, the feedback is more complex than two resistors—in these circuits, we use a DAC to perform the corresponding function instead of the resistor. When the rest of the circuit achieves loop gain in a manner similar to an op amp circuit, flaws in the DAC approach can be detrimental.

ADCs use component shuffling or calibration, which provides a way to deal with DAC component mismatches. These mashups or calibrations shift errors to higher frequencies, but also use more timing events and may increase jitter-related performance degradation. This ultimately results in a situation where the noise floor is contaminated by jitter effects, thereby reducing the effectiveness of noise shaping. Because the modulator can employ different DAC schemes as well as mixtures of them, such as return-to-zero and half-return-to-zero. An in-depth study of these scenarios for analysis and numerical simulation is beyond the scope of this article.

Regarding jitter in this article, we will simplify it graphically. Because of the jitter dependency issues within the ADC loop, some newer designs will provide frequency multipliers with the appropriate amount of phase noise on the chip. While this saves the system designer much work, note that the frequency multiplier still relies on a good external clock and a low-noise power supply. In these systems, one should consider reviewing the PLL literature for potential threats to the observed phase noise. Figure 8 shows the anti-jitter performance of different DACs, showing that discrete-time DAC operation has minimal impact.

图8. 离散时间 DAC 在某种程度上抗抖动，而在连续时间DAC中，窄脉冲将对抖动性能具有显著的影响

Modern continuous-time sigma-delta designs include on-board PLLs. They do not offer a wide range of clock speeds due to careful timing adjustments consistent with passive components. Some artificial methods can be used to expand the selection range of ADC conversion rates. This method uses sampling rate conversion. Sample rate conversion, while providing the advantages of digital circuits, increases power consumption, but these costs still make it a worthwhile alternative to highly tuned analog circuits. Many of Analog Devices' ADCs offer sample rate conversion options.

Another specific area where precise timing can impact performance is in switched capacitor filtering. When designing a precision ADC, you need to ensure that all interfering signals are eliminated or adequately attenuated. The ADC may provide specific embedded analog and digital filtering. The ADC's digital filtering has strong anti-jitter capabilities, while any form of clock analog filtering will be affected by jitter.

This is especially important when precision converters use more advanced front-end switches. Although switched capacitor filters may have advantages in theory, we can only refer to the abstract for further research and analysis.

One of the common schemes in converters is Correlated Double Sampling (CDS) . See Figure 9 to see how the CDS suppression quality performance changes over the clock at three different quality levels. The figure shows the signal near the stop band. Shown is a switched capacitor filter centered at 1 on the x-axis. The center of the plot is not suppressed by digital filtering and relies on an analog switched capacitor filter. A good quality clock is required to maintain good suppression levels. Even when measuring dc signals, jitter affects noise performance by aliasing downward interfering signals that should be filtered out by the switched capacitor filter on the silicon. The presence or absence of an onboard switched capacitor filter may not be explicitly mentioned in the data sheet.

Figure 9. Switched capacitor filtering performance and clock quality—mark-to-space ratio.

Practical guidance, root causes and common guesses

Now that we've shown a few situations where clocking can cause problems for you, let's look at techniques that can help you implement a system that minimizes the amount of jitter.

clock signal reflection

A high quality clock source has very fast rise and fall times. The advantage is reduced jitter noise during conversion. Unfortunately, the benefits of steep edges impose fairly stringent requirements for proper routing and termination. If a clock line is not terminated properly, the line will be affected by reflected waves that are added to the original clock signal. This process is very destructive and the associated jitter levels can easily take up hundreds of picoseconds. In extreme cases, the clock receiver can see additional edges that can cause the circuit to lock up.

Figure 10. Bad, better, and best circuit designs for clocks (in descending order).

One approach that may not make sense is to use an RC filter to slow down the edges and thus remove the high frequency content. It's even possible to use a sine wave as a clock source while waiting for a new PCB with 50Ω traces and terminations. Although the transition is relatively gradual and the duty cycle may be skewed by digital input hysteresis, this will reduce the reflected component of the jitter.

Power supply noise

The digital clock can be routed internally to the ADC through various buffers and/or level shifters before passing the edge to the sampling switch. If the ADC has an analog power pin, the level shifter used will become a source of jitter. Typically, the analog side of the chip will have high voltage devices with longer slew times, so the jitter sensitivity will be increased. Some well-designed devices separate more analog power on the board for clock and linear circuitry.

Figure 11. Sampling time affected by noise introduced by DVDD, AVDD, and different power domains between AGND and DGND

Decoupling Capacitors: Find the Right Product

Jitter caused by power supply noise will be reduced or amplified by decoupling circuits. Some sigma-delta modulators will do a lot of digital activity in analog and digital circuits. This can lead to non-characteristic spurs related to interference between the signal and the digital data. High frequency charge transfer should be limited to short loops near the device. To accommodate the shortest wiring, good designs use center pins along the elongated side of the chip. These limitations are not a common problem with amplifiers and low-frequency chips, which can have _VDD and VSS _pins in the corners , as shown on the left side of Figure 12. The PCB design should take full advantage of these features and place good quality capacitors near the pins.

Figure 12. Power supply schemes for linear circuits (left) and clock circuits (right).

Figure 13. Incorrect (left) and correct (right) placement of decoupling capacitors to reduce jitter.

Time dividers and clock signal isolators

Faster clocks have less jitter, so if power constraints allow, using a divider externally or internally to provide the required sample clock would be an improvement. When designing a system with an isolator, check its pulse width. If the duty cycle is suboptimal, skew can interfere with analog performance and, in extreme cases, may lock up the digital side of the IC. In precision ADCs, fiber optic clocks may not be needed, but using higher frequencies can provide last-bit performance. In Figure 14, the AD9573 uses 2.5GHz internally, with all 33MHz and 100MHz available for the same reason. If precise synchronization between ADCs is not required, a crystal circuit may have extremely robust single-digit and jitter performance. For precision ADCs, crystal amplifiers translate to better than 22-bit performance at 100 kHz input. This performance is hard to beat and explains why XTAL oscillators will remain in use for the foreseeable future.

Figure 14. Detailed functional block diagram of the AD9573.

Crosstalk from other signal sources

Another source of jitter is related to clock interference originating from external lines. If a clock source is incorrectly routed near a signal that is capable of coupling, this can have a dramatic impact on performance. If the source of interference is unrelated to the ADC operation and is random, it will significantly increase your jitter budget. Spurs will be observed if the clock is contaminated by digital signals associated with the ADC. For the slave ADC, the CLK line and SPI line can be independent clocks, but this can cause problems at the frequency defined in Equation 9 and aliasing back to the first Nyquist zone.

It is recommended to use frequency locked SPI and MCLK sources. Even with this precaution, SPI and MCLK may have spurs related to the pulse duty cycle of a given clock. For example, if the ADC decimates 128, and the SPI only reads 24 bits, there is some risk of creating beat frequencies associated with specific 1/(24t) and 1/(104t) measurements. Therefore, MCLK should be kept away from locked SPI lines as well as data lines.

Interfaces and other clocks

In Figure 15, various timing periods are marked, which can easily interfere with SFDR or cause jitter. If SPI communication is not frequency locked to MCLK, spurs may occur. Mastering layout techniques is your best defense in mitigating this problem. The frequencies appear as aliased downstream interference sources, but also as beat frequencies and intermodulation products. For example, if SPI is running at 16.01 MHz and MCLK is running at 16 MHz, spurs should occur at 10 kHz.

Figure 15. The presence of asynchronous communications and clocking requires mixed spurious troubleshooting and investigation efforts.

Besides good layout, another way to reduce spurs is to move them outside the relevant frequency band. If MCLK and SPI can be frequency locked, a lot of interference can be avoided. Even so, SPI still has issues with idle periods, resulting in busy ground, which can still cause interference. You can use the interface features to your advantage. Interface functions in the ADC provide status byte or cyclic redundancy check (CRC). This may provide a good way to suppress spurs with the added benefit of these capabilities. Idle clocks, and even unused CRC bytes, help fill the data frame evenly. You may choose to ignore the CRC and still get the benefits of using it. Of course, this also means extra power on the digital lines.

Figure 16. MCLK routing too close to switch mode PSU.

Figure 17. Local source MCLK with XTAL amplifier and SPI-related spurs.

Figure 18. Virtual CRC or status can be used to improve frames to eliminate spurs.

in conclusion

Analog Devices has released the AD7768-1, a high-precision ADC with sub-100 μV offset and flat frequency response up to 100 kHz. This ADC has been successfully used in system designs with SFDR in excess of 140 dB and has proven to have negligible jitter outside the audio band with full-scale inputs. It contains an on-chip RC oscillator that provides a reference point for debugging disturbed clock sources. Although this internal RC does not provide low jitter, it does provide a differential method to find spurious sources.

Figure 19. Spectrum of the AD7768-1 with properly designed PCB and clock circuitry.

The ADC implements internal switched capacitor filtering technology and also uses a clock divider to relieve the stress on the anti-aliasing filter. An internal clock divider ensures stable performance, enabling operation with an offset clock typically derived from an isolator. The power supply location is ideal for limiting external ESR/ESL effects through internal short junctions. Glitch suppression is implemented in the clock input pad. The application board performance scan shows a jitter of 30psrms, which can meet various application requirements. If you need to measure SFDR of 140+dB, the AD7768-1 can help you get the measurement very quickly and consume far less power than previous traditional power rail methods.

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