How to solve the problem of sensor signal conditioning? Here is some useful information for you~

Figure 1 shows a synchronous demodulation system for measuring the output signal of a sensor. The excitation signal fx is used as a carrier, and the sensor is modulated with amplitude, phase (or both) as a function of the parameter to be measured. The signal may be amplified and filtered before being modulated down to a DC state by a phase sensitive detector (PSD). The output filter (OF) limits the signal bandwidth to the frequency range of the parameter to be measured.

Figure 1. Synchronous demodulation system.

Noise at the sensor output can be caused by internal sources or external coupling. Low frequency (1/f) noise often limits the performance of the sensor or measurement electronics. Many sensors are also susceptible to low frequency environmental noise. Optical measurements are susceptible to background illumination; electromagnetic sensors are susceptible to power supply radiation. The freedom to choose the excitation frequency to avoid noise sources is an important advantage of synchronous demodulation.

Selecting an excitation frequency that reduces the effects of these noise sources is an important way to optimize system performance. The selected excitation frequency should have a low noise floor and be far enough away from the noise sources that proper filtering can reduce the noise to acceptable levels. Sensor excitation is often the largest piece of the power budget. If the sensor's sensitivity vs. frequency is known, power consumption can be reduced by exciting the sensor at a frequency with a higher sensitivity.

When there is absolutely no phase shift between the input and reference voltages, the relative phase is 0°, the switch output is DC, and the PSD output voltage is +1. As the relative phase increases, the switch output becomes a square wave with twice the reference frequency, and the duty cycle and average value decrease linearly. At a relative phase of 90°, the duty cycle is 50% and the average value is 0. At a relative phase of 180°, the PSD output voltage is –1. Figure 2b shows the average output values ​​of the PSD as the relative phase is swept from 0° to 360°, with square and sine wave input signals.

Figure 2. (a) PSD time domain waveform (b) PSD output average as a function of relative phase

The sine wave case is not as intuitive as the square wave case, but can be calculated by multiplying each term and breaking it down into addition and subtraction terms, as shown below:

As expected, the PSD generates a response at the fundamental frequency that is proportional to the cosine of the relative phase of the input signal, but it also generates a response to all odd harmonics of the signal. If the output filter is considered as part of a phase-sensitive detector, the signal transmission path looks like a series of bandpass filters centered on the odd harmonics of the reference signal. The bandwidth of the bandpass filters is determined by the bandwidth of the low-pass output filter. The PSD output response is the sum of these bandpass filters, as shown in Figure 3. The portion of the response that appears at dc falls within the passband of the output filter. The portion of the response that appears at the even harmonics of the reference frequency will be suppressed by the output filter.

Figure 3. Signal input spectrum contributing to PSD output.

At first glance, the infinite summation of harmonics aliasing into the output filter passband would appear to defeat this approach. However, since each harmonic term is scaled down by a factor of two and the noise of each harmonic adds in a square root of the sum of squares fashion, the effect of noise aliasing is mitigated. Assuming the noise spectral density of the input signal is constant, the noise effect of harmonic aliasing can be calculated.

Let Vn be the integrated noise of the transmission window centered on the fundamental frequency. The total RMS noise VT is:

Use a handy formula to sum a geometric series:

The increase in RMS noise caused by the harmonic window is:

Therefore, the RMS noise contributed by all harmonic windows only adds 11% (or 1dB) to the total noise. The output is still susceptible to the passband ripple of the bandpass filter, and the harmonic distortion of the sensor or electronics before the PSD will cause errors in the output signal. If these harmonic distortion terms are too large to be acceptable, they can be reduced using an antialiasing filter. The antialiasing and output filter requirements will be considered in the next design example.

There are many types of LVDTs and different methods of extracting position information. This circuit uses a 4-wire mode LVDT. The secondary outputs of the two LVDTs are connected so that their voltages are opposite, thus performing a subtraction. When the LVDT core is in the null position, the voltages on the secondary terminals are equal and the voltage difference across the windings is zero. As the core moves from the null position, the voltage difference across the secondary windings increases. The LVDT output voltage changes sign depending on the direction. The LVDT chosen for this example measures ±2.5 mm full-scale core displacement. The voltage transfer function is 0.25, which means that when the core is 2.5 mm off center, the differential output is equal to 250 mV for every volt applied to the primary.

Figure 4. Simplified LVDT position sensing circuit.

Figure 5. ADA2200 synchronous demodulator

The 4.92 MHz clock generated by the AD7192 24-bit Σ-Δ ADC is used as the master clock. The ADA2200 generates all the internal signals required for the filter and PSD clocks, and also generates the excitation signal on the RCLK pin. The device divides the master clock by 1024 to generate a 4.8 kHz signal to control the CMOS switch. The CMOS switch converts the low noise 3.3 V source into a square wave excitation signal for the LVDT. The 3.3 V supply for the excitation source is also used as the ADC reference voltage source, so any drift in the voltage source does not degrade the measurement accuracy. At full-scale displacement, the LVDT outputs a 1.6 V peak-to-peak output voltage.

Signal energy at odd multiples of the demodulated frequency will appear in the passband of the output filter. The FIR decimation filter implements antialiasing filtering and provides at least 50 dB attenuation for these frequencies.

The IIR filter can provide additional filtering or gain if needed. Since the IIR filter precedes the phase sensitive detector, its phase response will affect the PSD signal output bandwidth. This must be taken into account when designing the filter response.

This circuit uses the LPF built into the AD7192 Σ-Δ ADC. It can be programmed to have a sinc3 or sinc4 response, with the transfer function being zero at multiples of the output data rate.

The PSD output spurs can be suppressed by setting the ADC's output data rate to the demodulation frequency. The ADC's programmable output data rate acts as a selectable bandwidth output filter. The available output data rates (fDATA) are 4.8 kHz/n, where 1 ≤ n ≤ 1023. Therefore, the ADC averages the demodulator output over n demodulation clock cycles for each output data value. Since the host clock and ADC clock are synchronized, the zeros of the ADC output filter transfer function will fall directly on every harmonic of the modulation frequency and suppress all output spurs for any value of n.

Figure 6 shows the sinc3 transfer function normalized to the ADC output data rate.

The programmable output data rate offers a straightforward trade-off between noise and bandwidth/settling time. The output filter noise bandwidth is 0.3 × fDATA, the 3 dB frequency is 0.272 × fDATA, and the settling time is 3/fDATA.

At the maximum 4.8 kHz output data rate, the ADC digital filter has a 3 dB bandwidth of approximately 1.3 kHz. Up to this frequency, the RC filter between the demodulator and ADC is relatively flat, minimizing the bandwidth requirements of the ADC. In systems with lower maximum data rates, the RC filter corner frequency can be reduced proportionally.

Table 1. Noise Performance vs. Bandwidth

If the ADA2200 output noise is independent of frequency, the effective number of bits is expected to increase by one bit for every 4× decrease in the output data rate. ENOB does not increase as much at lower output data rates due to the 1/f noise of the ADA2200 output driver; this noise dominates the noise floor at lower output data rates.

Figure 7. Position linearity error vs. LVDT core displacement.

The E-Series LVDT used for circuit evaluation has a linearity rating of ±0.5% (±2.5 mm displacement range). The circuit performance exceeds the specifications for the LVDT.