How to evaluate the phase noise of distributed PLL systems? Here is a good method~

In a distributed system, common noise sources are correlated, while distributed noise sources, if uncorrelated, will decrease when the RF signal combines. For most components in a system, this can be evaluated quite intuitively. For a phase-locked loop, each component in the loop has a noise transfer function associated with it, and their contribution is a function of the control loop as well as any frequency translation. This can add complexity when trying to evaluate the combined phase noise output. This article builds on known phase-locked loop modeling methods and an evaluation of correlated and uncorrelated contributions to present a method for tracking distributed PLL contributions at different frequency offsets.

As with any radio system, the implementation of LO generation for both the receiver and the exciter needs to be carefully designed. As digital beamforming becomes more prevalent in phased array antenna systems, the design becomes more complex with the need to distribute the LO signal and reference frequency among a large number of distributed receivers and exciters.

The trade-offs that need to be made at the system architecture level include distributing the required LO frequency or distributing a lower frequency reference and generating the required LO in a physical location close to the point of use. Local LO generation via a phase-locked loop is a highly integrated, off-the-shelf option. The next challenge is to evaluate the system-level phase noise from the various distributed components as well as the centralized components.

A system using distributed phase-locked loops is shown in Figure 1. A common reference frequency is distributed to multiple phase-locked loops, each generating an output frequency. The LO output in Figure 1a is assumed to be the LO input to the mixer in Figure 1b.

Figure 1. Distributed phase-locked loop system. Each oscillator is phase-locked to a common reference oscillator. LO signals from 1 to N are applied to the LO ports of the mixers shown in the phased array.

A challenge for system designers is to track noise contributions from distributed systems, understand correlated and uncorrelated noise sources, and estimate the overall system noise. In phase-locked loops, this challenge becomes even more severe because the noise transfer function is a function of the frequency translation and loop bandwidth settings in the phase-locked loop.

Figure 2. Phase noise measurement of two combined phase-locked loops.

Figure 3. Typical phase-locked loop phase noise analysis showing the noise contributions of all components. The total noise is the sum of all contributing factors.

To examine the effect of a distributed phase-locked loop, first derive the reference contribution and the contributions of the remaining PLL components from the PLL model.

Figure 4. Getting started with a distributed PLL phase noise modeling approach: The phase noise contributions of the reference oscillator and all other components in the PLL except the reference oscillator are extracted from the PLL model. The combined phase noise as a function of the number of distributed PLLs assumes that the reference noise is correlated and the noise contributions distributed among the multiple PLLs are uncorrelated.

The example shown in Figure 4 makes simplified assumptions about the reference oscillator distribution. In a true system analysis, the system designer should also consider the noise contributions in the reference oscillator distribution, which will degrade the overall result. However, a simplified analysis like this is very useful to understand how architectural trade-offs can affect the overall phase noise performance of the system. Next, let’s look at the impact of phase noise in a distributed system.

Figure 5. Distributed wideband PLL with PLL IC in distribution.

There are some features of this model that are worth noting. Assuming a high performance crystal oscillator with a nominal frequency of 100 MHz, the individual contribution from the central oscillator is reflected in the higher end crystal oscillator available, although not necessarily the best and most expensive choice available. While the central oscillator output actually fans out to a limited number of distributed PLLs, these PLLs fan out again to some practical limit and repeat to achieve full distribution in the system. For the distributed contributions in this example, 16 distributed components are assumed, and then they are assumed to fan out again. The individual contribution of the distributed circuit shown in the lower left corner is the noise of the PLL components without the reference oscillator contribution. The distribution in this example is assumed to be at the same frequency as the source oscillator, and the noise contributors are chosen based on typical ICs available for this function.

The wideband PLL assumes a nominal S-band frequency and is set up with a 1 MHz loop bandwidth (as wide as the actual loop bandwidth can be) for fast tuning.

It is important to note that these models were chosen to represent possible real-world situations and illustrate cumulative effects in an array. It is expected that any detailed design may improve a specific PLL noise curve, and this analysis is intended to help determine from an engineering perspective where design resources should be allocated to achieve the best overall effect, rather than to make firm judgments relative to available components.

The bottom right plot of Figure 5 calculates the total combined phase noise of the LO distribution. The PLL noise transfer function of each contributor is applied, all scaled to the output frequency, and the effect of the PLL loop bandwidth is also included. The number of systems is also included and is assumed to be uncorrelated, so this contribution is reduced by 10logN. Assuming the number of distributions is 16, the distribution contribution is reduced by 10log16 as previously mentioned. In practice, this contribution is further reduced as the distribution is repeated. However, the additional noise contributions are less significant. For fan-out distributions in large arrays, the noise will be dominated by the first set of active devices. In the case of 16 sets of fan-out, if each active device is the input to 16 other active devices, then an additional distribution layer of 16 devices will only reduce by ~0.25 dB if all devices are uncorrelated. If this distribution is continued, the overall contribution will be even smaller. Therefore, to simplify the analysis, this effect is not considered and the noise contribution of the distribution is calculated for the first 16 parallel distribution components.

The resulting curves illustrate several effects. Similar to the single PLL model, the close-in noise is dominated by the reference frequency, the far-out noise is dominated by the VCO, and the far-out noise is improved when the uncorrelated VCOs are combined. This is fairly intuitive. Less intuitive is that the model's values ​​are weighted more heavily at offset frequencies dominated by the choice in the distribution. This result leads to considering a second example with a lower noise distribution and narrower PLL loop bandwidth.

Figure 6 shows a different approach. The same low noise crystal oscillator is used as the reference. But it is distributed through RF amplifiers instead of retiming and resynchronizing through PLLs. A fixed frequency distributed PLL is chosen. This has two effects: the VCO can be inherently better with a single frequency and narrow tuning range, and the loop bandwidth can be made narrower. The lower left plot shows the individual contributors. The central oscillator is the same as in the previous example. Note the distributed amplifiers: they are not particularly high performance when considering low phase noise amplifiers, but much better than using a PLL LC (as in the previous example). With a better VCO and narrower loop bandwidth, the distributed PLL improves at higher offset frequencies, but is actually worse than the wideband PLL example at intermediate frequencies of ~1 kHz. The lower right shows the combined result: the reference oscillator dominates at low frequencies, but above the loop bandwidth, the performance is dominated by the distributed PLLs, and improves with the array size and number of distributed PLLs.

Figure 6. Distributed narrowband PLL with amplifiers in the distribution.

A comparison between these two examples is shown in Figure 7. Note the large difference in the ~2 kHz to 5 kHz offset frequency range.

Figure 7. Comparison between Figure 5 and Figure 6, showing the wide range of system-level performance based on the selected distribution and architecture.

PLL Bandwidth

Traditional phase-locked loop designs optimized for phase noise set the loop bandwidth to an offset frequency that minimizes the overall phase noise profile. This is typically the frequency where the reference oscillator phase noise normalized to the output frequency intersects the VCO phase noise. For a distributed system with multiple phase-locked loops, this may not be the optimal loop bandwidth. The number of distributed components also needs to be considered.

To achieve optimum LO noise in a system using a distributed phase-locked loop implementation, a narrow loop bandwidth is required to minimize the reference oscillator's correlated noise contribution.

For systems that require fast tuning of the PLL, the loop bandwidth is often widened to optimize speed. Unfortunately, this is counterproductive to optimizing the distributed phase noise contribution. One option to overcome this is to place a distributed narrowband cleanup loop before the wideband loop to reduce the offset frequency where the reference and distributed noise are related.

Large Arrays

For systems using thousands of channels, significant improvements can be achieved if the contributions of the distributed components remain uncorrelated. The main considerations may revolve around the choice of reference oscillators and maintaining a low noise distribution system for the distributed receivers and exciters.

Direct Sampling System

As GSPS converters continue to gain popularity with increasing speeds and RF input bandwidths, direct sampling systems are becoming available at microwave frequencies. This leads to an interesting trade-off. The data converters only need a single clock frequency, and RF tuning is done entirely in the digital domain. By limiting the tuning range, VCOs can be built with higher phase noise performance. This also allows the loop bandwidth of the PLL that creates the data converter clock to be reduced. Lower loop bandwidth reduces the noise transfer function of the reference oscillator to lower offset frequencies, reducing its contribution in the system. This, combined with improved VCOs, can bring benefits to distributed systems in some cases, even if single-channel comparisons seem to favor alternative architectures.

For separate PLL and VCO configurations, the ADF41513 operates up to 26 GHz and features an advanced PLL phase noise FOM of -234dBc/Hz. Sometimes a consideration in selecting a PLL IC is to operate the phase detector at as high a frequency as possible, minimizing the noise in the loop from multiplying 20logN to the output frequency. The PFDs used in the HMC440, HMC4069, HMC698, and HMC699 operate up to 1.3 GHz. For VCOs, the 2018 selection guide lists dozens of VCO options ranging from 2 GHz to 26 GHz.

For direct sampling options, both ADCs and DACs have been released. Products support direct sampling in L-band and S-band. The ADC has a higher input frequency bandwidth to support direct sampling in C-band. The AD9208 is a dual 3 GSPS ADC with an input frequency of 9 GHz, supporting sampling in the upper Nyquist zone. The AD9213 is a single 10 GSPS ADC that supports receivers with larger instantaneous bandwidth. For DACs, the AD917x family uses a dual 12 GSPS DAC and the AD916x family uses a single 12 GSPS DAC that are optimized for lower residual phase noise and better SFDR. Both families support L-band and S-band waveform generation.

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