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Design preservation using SmartCompile and Xilinx design tools

2013-09-20
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Using design preservation techniques such as partitions, automatic naming, and topology matching can potentially reduce the time it takes to resolve problems by months. By Eric Shiflet and Kate Kelley Xilinx In FPGA environments, design preservation is a complex implementation challenge that requires preservation of items such as a design\'s HDL description, a module\'s synthesized netlist, placement information in constraint files, and configuration data in local bitfiles. Xilinx\'s Integrated Software Environment (ISE) 9.1i software features new SmartCompile technology, which includes two new methods—SmartGuide and Partitions—that preserve design implementation data such as placement or routing and can reduce the time it takes to resolve problems.

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