This paper conducts an in-depth study and analysis on the structure, interface and timing of a DDR2 SDRAM controller, summarizes some key technical characteristics of the controller, and then adopts a top-down (TOP-IX) design method to implement the controller with Verilog hardware description language. It is then simulated by software function on Modelsim 6.1, synthesized by Synopsys\' DC, and hardware verified by Altera\'s FPGA. The results show that the controller is fully capable of controlling DDR2 SDRAM.
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