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Design of IS95 cdma2000 Timing Extraction Module

  • 2013-09-22
  • 146.93KB
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An IS95/CDMA2000 timing module is designed. The zero-IF receiving chip SA9521 is used as the core to demodulate the RF signal to the I/Q baseband. Xilinx\'s Spartan-3A DSP series FPGA XC3SD1800A is used for baseband processing. By receiving the pilot channel and synchronization channel in the IS95/CDMA2000 forward link, high-precision second pulse and local time are output. The second pulse accuracy is better than 1 microsecond.

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