Abstract: This paper briefly introduces the basic concepts of image edge detection and discusses the basic model of its hardware implementation. It analyzes its key arithmetic units, adopts a variety of optimization measures and introduces pipeline design methods to meet the requirements of high-speed applications. It proposes three different FIR filter implementation structures. Finally, it completes FPGA and ASIC design, compares the implementation data of different structures and gives a conclusion. The implementation results show that this design can meet the application of high-speed systems. Keywords: edge detection; FIR filter; pipeline design; carry-lookahead addition; FPGA
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