PACE1753
SINGLE CHIP, 40MHz
CMOS MMU/COMBO
FEATURES
Implements the MIL-STD-1750A Instruction Set
Architecture for Memory Management and
Protection of up to 1 Megaword. All mapping
memory (10,240 bits) for both the MMU and
BPU functions are included on the chip.
Designed to interface memory to the
PACE1750A/AE 16-bit, 40 MHz processor.
Systems can be designed where no WAIT
states are required up to 40 MHz clock rates
when using these PACE products.
System performance and device count are
optimized when used with the PACE1754
Processor Interface Circuit (PIC).
Provides the following additional functions:
— EDAC, Error Detection and Correction—or
parity generation and detection
— Correct data register—for diagnostics
— First memory failing address register
— Illegal address error detection—
programmable
— Multi-Master arbitration
8-bit extended address latches and drivers on
chip
Information bus and EDAC transceivers on chip
20, 30 and 40 MHz operation over the Military
Temperature Range
Single 5V ± 10% Power Supply
Power Dissipation over Military Temperature
Range (P
D
Outputs Open)
< 0.20 watts at 20 MHz
< 0.30 watts at 30 MHz
< 0.40 watts at 40 MHz
Available in:
— 64-Pin DIP or Gull Wing (50 Mil Pin centers)
— 68-Pin Pin Grid Array (PGA) (100 Mil centers)
— 68-Lead Quad Pack (Leaded Chip Carrier)
MEMORY MANAGEMENT UNIT AND
BLOCK PROTECT UNIT “COMBO” —
FUNCTIONAL DESCRIPTION
The PACE1753 (COMBO) is a support chip for the
PACE1750A/AE microprocessor family. It provides the
following supporting functions to the system:
1. Memory management and access protection for up
to 1M words.
2 Physical memory write protection for up to 1M words
memory in pages of 1K words each. Separate
protection is provided for the CPU and for DMA in
systems which include DMA.
3. Detection of illegal l/O accesses (as defined by MIL-
STD-1750A) or access to an unimplemented block
of memory. In each case an error flag is generated
to the processor.
4 Detection of double errors on the data bus and
correction of single errors. An error signal is generated
to the processor when a multiple error is detected.
5. RDYA generation. Up to three wait states can be
inserted in the address phase of the bus by generating
a not-ready, RDYA low signal. The number of wait
states required can be programmed in an internal
register in the COMBO.
6. Bus arbitration for up to 4 masters. Arbitration is
done on a fixed priority basis (i.e. by interconnection
of hardware). (In 68 pin package only).
Document #
MICRO-4
REV D
Revised November 2005
PACE1753
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage Range
Input Voltage Range
Storage Temperature Range
Input Current Range
Current applied to any output
3
Maximum Power Dissipation
2
Lead Temperature Range
(soldering 10 seconds)
Thermal resistance (θ
JC
):
4
Cases X and T
Cases Y and U
Case Z
0.5V to +7.0V
0.5V to V
CC
+ 0.5V
–65°C to +150°C
–30mA to +5mA
150mA
1.5W
300°C
8°C/W
5°C/W
6°C/W
RECOMMENDED OPERATING
CONDITIONS
Supply Voltage Range
Case Operating
Temperature Range
Operating Maximum Power
Dissipation (Outputs Open)
Device Type 20MHz
Device Type 30MHz
Device Type 40MHz
4.5V to +5.5V
–55°C to +125°C
0.20W
0.30W
0.40W
Notes
1. Stresses above the absolute maximum rating may cause
permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2. Must withstand the added power dissipation due to short circuit
test e.g., I
OS
.
3. Duration 1 second or less.
4. Device Type Definitions from 5962-89505 SMD:
Case X: Dual In-Line
Case T: Dual In-Line with Gull-Wing Leads
Case Y: Leaded Chip Carrier with Gull-Wing Leads
Case U: Leaded Chip Carrier with Unformed Leads
Case Z: Pin Grid Array
Document #
MICRO-4
REV D
Page 2 of 21
PACE1753
DC ELECTRICAL SPECIFICATIONS
(Over recommended operating conditions)
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
V
OL
I
IH
Parameter
Input HIGH Voltage
Input LOW Voltage
2
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage,
except EXT ADR
0
– EXT ADR
7
Output LOW Voltage,
EXT ADR
0
– EXT ADR
7
Input HIGH Current,
except IB
0
– IB
15
,
EDC
0
– EDC
5
,
EXT ADR
0
– EXT ADR
7
Input HIGH Current,
IB
0
– IB
15
, EDC
0
– EDC
5
,
EXT ADR
0
– EXT ADR
7
Input LOW Current,
except IB
0
– IB
15
,
EDC
0
– EDC
5
,
EXT ADR
0
– EXT ADR
7
Input LOW Current,
IB
0
– IB
15
, EDC
0
– EDC
5
,
EXT ADR
0
– EXT ADR
7
Output Three-State Current
Output Three-State Current
Quiescent Power Supply
Current (CMOS Input
Levels, Active)
Quiescent Power Supply
Current (TTL Input
Levels, Active)
Dynamic Power Supply
I
CCD
I
OS
C
IN
C
OUT
Current
Output Short Circuit Current
3
Input Capacitance
Output/Bi-directional
Capacitance
–25
10
15
2.4
V
CC
– 0.2
0.5
0.2
0.5
0.2
10
Min
2.0
–0.5
Max
V
CC
+ 0.5
0.8
–1.2
Unit
V
V
V
V
V
V
V
V
V
µA
V
CC
= 4.5V, I
IN
= –18mA
V
CC
= 4.5V,
V
IN
= 0.8V, 2.0V
V
CC
= 4.5V,
V
IN
= 0.8V, 2.0V
V
CC
= 4.5V,
V
IN
= 0.8V, 2.0V
V
IN
= V
CC
,
V
CC
= 5.5V
V
IN
= V
CC
,
V
CC
= 5.5V
I
OH
= –8.0mA
I
OH
= –300µA
I
OL
= 8.0mA
I
OL
= 300µA
I
OL
= 20.0mA
I
OL
= 300µA
Conditions
1
I
IH
50
µA
I
IL
–10
µA
V
IN
= GND,
V
CC
= 5.5V
V
IN
= GND,
V
CC
= 5.5V
V
OUT
= 2.4V, V
CC
= 5.5V
V
OUT
= 0.5V, V
CC
= 5.5V
V
IN
< 0.2V or < V
CC
– 0.2V
f = 0MHz, Outputs Open,
V
CC
= 5.5V
V
IN
= 3.4V, f = 0MHz,
All Inputs, Outputs Open,
V
CC
= 5.5V
V
CC
= 0V to V
CC
,
tr = tf = 2.5 ns,
Outputs Open,
V
CC
= 5.5V
I
IL
I
OZH
I
OZL
I
CCQC
–50
50
–50
60
µA
µA
µA
mA
I
CCQT
110
40
50
60
mA
mA
mA
mA
mA
pF
pF
F = 20MHz
F = 30MHz
F = 40MHz
V
OUT
= GND, V
CC
= 5.5V
Inputs Only
Outputs Only
(Including I/O Buffers)
Notes
1. 4.5V
≤
V
CC
≤
5.5V, –55°C
≤
T
C
≤
+125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. V
IL
= –3.0V for pulse widths less than or equal to 20ns.
3. Duration of the short should not exceed one second; only one output may be shorted at a time.
Document #
MICRO-4
REV D
Page 3 of 21
PACE1753
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V)
20 MHz
Symbol
TD/I (EXT ADR)
V
Parameter
MMU Cache Hit
Min
Max
25
25
25
35
25
30
25
25
25
25
35
35
35
35
30
30
34
50
25
25
25
50
40
45
25
32
30MHz
Min
Max
23
20
20
30
20
25
20
20
22
20
25
25
25
25
25
28
30
45
20
22
22
45
35
35
20
30
40 MHz
Min
Max
23
16
19
25
12
23
12
12
18
16
18
18
18
18
17
25
25
40
16
18
18
40
30
30
20
23
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSTRBD (EXT
ADR ERR)
L
External Address Error
TC (IBD CORR)
IBD
V
(SING ERR)
H
TC (SING ERR)
L
TIBD
V
(EDC GEN)
V
TSTRBD (EX RDY)
L
TC (EX RDY)
H
TC (WR
PROT)
L
TSTRBD
H
(WR
PROT)
H
TC (GNT1)
H
TC (GNT0)
L
TC (GNT0)
H
TC (GNT1)
L
TC (RDYA)
TFC (IB OUT)
V
TIBD
IN
(MEM
PAR ERR)
TC (MEM
PRT ERR)
TSTRBD (WR
PROT)
TC (WR
PROT)
L
TSTRBD
H
(WR
PROT)
H
TD/I (PROT FLAG)
TD/I (PROT FLAG)
TC (PROT FLAG)
TC (PROT FLAG)
TC (EXT ADR)
Error Correction Read Cycle
Error Correction Read Cycle
Error Correction Read Cycle
EDAC or Parity Write Cycle
MMU Cache Miss
MMU Cache Miss
MMU Cache Miss
MMU Cache Miss
Arbiter LOW to HIGH Priority
Arbiter LOW to HIGH Priority
Arbiter HIGH to LOW Priority
Arbiter HIGH to LOW Priority
Address Ready
Clock to IB Out Valid (I/O Read)
Parity Mode
Memory Protect Error
Write Protect Cache Hit
Write Protect Cache Miss
Write Protect Cache Miss
Cache Hit (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Cache Miss (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Clock to EXT ADR Valid (Miss)
Notes:
1. 4.5V
≤
V
CC
≤
5.5V, –55°C
≤
T
C
≤
+125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. V
IL
= –3.0V for pulse widths less than or equal to 20ns.
3. Duration of the short should not exceed one second; only one output may be shorted at a time.
4. Pulse width of
WR PROT/PROT
FLAG shall be
≥
80% of
STRBD
pulse width.
Document #
MICRO-4
REV D
Page 4 of 21
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