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HY57V641620ESTP-7

Description
64mb synchronous dram based on 1M x 4bank x16 I/O
Categorystorage    storage   
File Size109KB,13 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Environmental Compliance
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HY57V641620ESTP-7 Overview

64mb synchronous dram based on 1M x 4bank x16 I/O

HY57V641620ESTP-7 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSK Hynix
Parts packaging codeTSOP2
package instructionTSOP2, TSOP54,.46,32
Contacts54
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)143 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G54
JESD-609 codee6
length22.238 mm
memory density67108864 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals54
word count4194304 words
character code4000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP54,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1.194 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.002 A
Maximum slew rate0.18 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Bismuth (Sn/Bi)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
width10.16 mm
64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O
Document Title
4Bank x 1M x 16bits Synchronous DRAM
Revision History
Revision No.
First Version Release
1.0
1. Changed tOH: 2.0 --> 2.5
[tCK = 7 & 7.5 (CL3) Product]
1. Changed Input High/Low Voltage (Page 08)
2. Changed DC characteristics (Page 09)
- IDD2NS: 18mA -> 15mA
- IDD5:210 / 195 / 180mA -> 170 / 160 / 150mA
[Speed 200 / 166 / 143 / 133MHz]
3. Changed Clock High / Low pulse width Time (Page 11)
4. Changed tAC Time (Page11)
5. Changed tRRD Time (Page12)
1. Corrected Revision No.: 2.0 -> 1.1
2. Deleted Remark at Revision History
3. Corrected AC OPERATING CONDITION
- CL 50pF -> 30pF
4. Changed DC OPERATING CONDITION
- VIH MAX VDDQ+2.0 -> VDDQ+0.3 and Typ 3.3 -> 3.0
- VIL MIN VSSQ-2.0 -> -0.3
1. Modified note for Super Low Power in ORDERING INFORMATION
1. Corrected PIN ASSIGNMENT A12 to NC
1. Corrected comments for overshoot and undershoot
Nov. 2004
History
Draft Date
Remark
1.1
Dec. 2004
1.2
Dec. 2004
1.3
1.4
1.5
Jan. 2005
Jan. 2005
Feb. 2005
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.5 / Feb. 2005
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