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935320728557

Description
Power Supply Management Circuit
CategoryPower/power management    The power supply circuit   
File Size2MB,94 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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935320728557 Overview

Power Supply Management Circuit

935320728557 Parametric

Parameter NameAttribute value
Objectid8367127424
package instruction,
Reach Compliance Codeunknown
ECCN codeEAR99
Analog Integrated Circuits - Other TypesPOWER SUPPLY MANAGEMENT CIRCUIT
NXP Semiconductors
Advance Information
Document Number: MC33909
Rev. 4.0, 8/2016
System basis chip with DC/DC and
multiple switch-to-ground interface
This SMARTMOS IC integrates the common functionality of system basis chips
with switch detection inputs. The device works as an advanced power
management unit for the MCU and additional integrated circuits such as
sensors, CAN transceivers, and eXtreme switches. It has one built-in enhanced
high-speed CAN interface (ISO 11898-2 and -5), with local and bus failure
diagnostics, protection and fail-safe operation mode, and includes four LINs,
compatible with specification 2.1 and SAEJ2602-2.
The IC starts operating when the VBATP (reverse battery protected) pin
reaches 5.3 V maximum. The device requires a reverse blocking ultrafast or
Schottky diode for operation. The VPRE supply operating in Buck/Boost mode
allows functional operation of the IC from 2.5 V to 35 V on VBATP. The VPRE
pin supplies the source voltage for the VDD, VAUX, CAN5V, and SG power
rails.
Switch-to-ground inputs are available for switch detection and supply
configurable pulsed wetting current, with low sustain current levels for
improved thermal and power management. The IC can be programmed to
wake-up when a change of state is detected on any input. The device also
implements an innovative and advanced fail-safe state machine and concept
solution.
Features
• VDD rail (3.3 V or 5.0 V) operates down to 2.5 V on VBATP (provided by
V
PRE
Buck/Boost)
• VAUX rail (3.3 V or 5.0 V) capable of surviving short-to-battery (40 V)
conditions
• Low Q current operation for low-power sleep mode, typ. 125
μA
• Secured SPI and advanced watchdog
• SAFE_B pin for limp home mode
• Six switch to GND inputs with selectable wake-up in change of state
• Analog multiplexer
33909
SYSTEM BASIS CHIP
AD SUFFIX (PB-FREE)
48 PIN LQFP-EP
98ASA00737D
Applications
• Front/rear body controllers
• Gateway modules
• Electric power steering
• Power train
VSW
VPREGATE
VPRE VAUXE VAUXB VAUX
VDDE
VDDB
VDD
V
BAT
V
BAT
PI Filter
BOOT
VBAT_SMPS
VBATP
VBATSNS
WDI
SG0
SG1
SG2
SG3
SG4
SG5
CANH
VDD
SAFE_B
AMUX
RST_B
INT_B
MOSI
MISO
SCLK
CS_B
RXD_L0:RXD_L3
TXD_L0:TXD_L3
RXD_C
TXD_C
CAN5V
MCU
SPI
CAN Bus
VBATP
CANL
LIN_0
LIN_1
LIN_2
LIN_3
LIN Bus
LIN Bus
LIN Bus
LIN Bus
GND LIN
GND
CANGND
Figure 1. 33909AD simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© 2016 NXP B.V.
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