PEX 8612-BB50RBC F datasheet, PDF

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PEX 8612-BB50RBC F: Descriptionpci interface IC 12 lane, 3 port pci express gen 2 switch; Categorysemiconductor Other integrated circuit (IC); File Size170KB，4 Pages; ManufacturerPLX Technology, Inc. (Broadcom ); Environmental Compliance

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PEX 8612-BB50RBC F Overview

pci interface IC 12 lane, 3 port pci express gen 2 switch

PEX 8612-BB50RBC F Parametric

Parameter Name	Attribute value
Manufacture	PLX Technology
Product Category	PCI Interface IC
RoHS	Yes
Type	Switch - PCIe
Number of Lanes	12 Lane
Number of Ports	3 P
Maximum Operating Temperature	+ 70 C
Mounting Style	SMD/SMT
Package / Case	FCBGA-324
Minimum Operating Temperature	0 C
Packaging	Tray
Factory Pack Quantity	84
Versi	Gen2

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Version 1.0 2009

Features

PEX 8612 Vitals

12-lane, 3-port PCIe Gen2 switch

Integrated 5.0 GT/s SerDes

19 x 19mm

, 324-pin FCBGA package

Typical Power: 1.6 Watts

PEX 8612

PCIe Gen2, 5.0GT/s 12-lane, 3-port Switch

The

ExpressLane

PEX 8612 device offers PCI Express switching

capability enabling users to add scalable high bandwidth, non-blocking

interconnection to a wide variety of applications including

workstations, storage systems, communications platforms,

embedded systems, and intelligent I/O modules.

The PEX 8612 is

well suited for

fan-out, aggregation, and peer-to-peer applications.

High Performance & Low Packet Latency

The PEX 8612 architecture supports packet

cut-thru with a maximum

latency of 170ns (x4 to x4).

This, combined with large packet memory and

non-blocking internal switch architecture, provides full line rate on all ports

for performance-hungry applications such as

servers

and

switch fabrics.

The low latency enables applications to achieve high throughput and

performance. In addition to low latency, the device supports a

max payload

size of 2048 bytes,

enabling the user to achieve even higher throughput.

Data Integrity

The PEX 8612 provides

end-to-end CRC

(ECRC) protection and

Poison bit

support to enable designs that require

end-to-end data integrity.

PLX also

supports data path parity and memory (RAM) error correction as packets

pass through the switch.

Flexible Register & Port Configuration

The PEX 8612’s 3 ports can be configured to lane widths of x1, x2, or x4.

Flexible buffer allocation, along with the device's

flexible packet flow

control,

maximizes throughput for applications where more traffic flows in

the downstream, rather than upstream, direction. Any port can be designated

as the upstream port, which

can be changed dynamically.

The PEX 8612 also provides

several ways to configure its

registers. The device can be

PEX 8612

configured through

strapping pins,

interface,

host software, or

an optional serial EEPROM.

This allows for easy debug

during the development

phase, performance

monitoring during the

PEX 8612

operation phase, and driver

or software upgrade. Figure

1 shows some of the

PEX 8612’s common port

Figure 1. Common Port Configurations

configurations.

PEX 8612 Key Features

Standards Compliant

PCI Express Base Specification, r2.0

(backwards compatible w/ PCIe r1.0a/1.1)

PCI Power Management Spec, r1.2

Microsoft Vista Compliant

Supports Access Control Services

Dynamic link-width control

Dynamic SerDes speed control

High Performance

Non-blocking switch fabric

Full line rate on all ports

Packet Cut-Thru with 170ns max packet

latency (x4 to x4)

2KB Max Payload Size

Read Pacing (bandwidth throttling)

Dual-Cast

Flexible Configuration

Ports configurable as x1, x2, x4

Registers configurable with strapping

pins, EEPROM, I

C, or host software

Lane and polarity reversal

Compatible with PCIe 1.0a PM

Dual-Host & Fail-Over Support

Configurable Non-Transparent port

Moveable upstream port

Crosslink port capability

Quality of Service (QoS)

Eight traffic classes per port

Weighted round-robin source

port arbitration

Reliability, Availability, Serviceability

2 Hot Plug Ports with native HP Signals

All ports hot plug capable thru I

(Hot Plug Controller on every port)

ECRC and Poison bit support

Data Path parity

Memory (RAM) Error Correction

INTA# and FATAL_ERR# signals

Advanced Error Reporting

Port Status bits and GPIO available

Per port error diagnostics

Performance Monitoring

•

Per port payload & header counters

PEX 8612-BB50RBC F Related Products

	PEX 8612-BB50RBC F	PEX 8612-BB50BC F	PEX 8612-BB50BC
Description	pci interface IC 12 lane, 3 port pci express gen 2 switch	Peripheral drives and components (pci) 12 lane, 3 port pci express gen 2 switch	Peripheral drives and components (pci) 12 lane, 3 port pci express gen 2 switch
Product Category	PCI Interface IC	Peripheral Drivers and Components (PCI)	Peripheral Drivers and Components (PCI)
RoHS	Yes	yes	no
Maker	-	PLX Technology, Inc. (Broadcom )	PLX Technology, Inc. (Broadcom )
Package/box	-	HFCBGA-324	HFCBGA-324
Encapsulation	-	Tray	Tray
Installation style	-	SMD/SMT	SMD/SMT

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