Some things about logic analyzer design

w494143467

Some things about logic analyzer design [Copy link]

 

 

I wonder if anyone has made a logic analyzer. I want to make a DIY logic analyzer. I have a question about the lower computer. If I use the serial port to communicate with the upper computer, what should the data format be? It's OK for a single channel, but what if it's multi-channel? This communication format seems to be a bit troublesome. I have thought of several solutions, but they don't seem to be suitable at high speeds. So I want to ask if there is a relatively suitable communication protocol, mainly to transmit the current pin status to the upper computer. The upper computer has not been made yet, so there is no problem yet. I want to solve the problem of the lower computer first.

tinnu

The serial port speed is not fast enough, usually USB is used, and it is HS, FS is too slow

w494143467

tinnu posted on 2020-10-26 20:13 The serial port speed is not fast enough, usually USB is used, and it is HS, FS is all lagging behind

In this case, the development of the upper computer is still quite troublesome. Do you have any opinions on the protocol?

littleshrimp

EBAZ4205, a development board that costs more than ten yuan, uses VIVADO and can be simply configured as a multi-channel logic analyzer.

mig29

The simplified version is to read the port in a loop, one channel corresponds to one bit, and 8 channels are one byte. According to certain trigger conditions, the memory is full and then uploaded to the PC. (It is easier to use an 8-bit machine because the execution time of the assembly instruction is fixed. Now 32-bit machines all have pipelines, and it is difficult to accurately calculate the time when encountering a jump instruction).

Just use this as a toy for study. For a practical version, search for seleae on Taobao. It costs less than 30 yuan.

freebsder

The format is not the problem, the problem is what to use to transmit. Check libusb.

shipeng

You don't need real-time communication, right? According to the logic analyzers I have used, they all record data for a period of time after the trigger is started, then transmit the data to the host computer, and then wait for the next start trigger.

w494143467

shipeng posted on 2020-10-27 08:27 You don't need real-time communication. According to the logic analyzers I have used, they all record data for a period of time after the trigger is started and then transmit the data to...

Are all the data transmitted? Or only the valid data? I also bought a logic analyzer and will try it out later.

大牛哥

I think it is best to use an external acquisition chip to complete the simple but resource-intensive operation of shifting.

w494143467

littleshrimp posted on 2020-10-26 22:01 EBAZ4205, a development board that costs more than ten yuan, uses VIVADO and is simply configured to be a multi-channel logic analyzer

I checked this development board, but it seems that it is not available on Taobao...

w494143467

mig29 posted on 2020-10-26 23:17 The simple version is to read the port in a loop, one channel corresponds to one bit, 8 channels are one byte, according to certain trigger conditions, upload to P after the memory is full...

Ok, I'll buy it and try it out when the time comes. I'll first buy an on-site logic analyzer to see what chip is inside.

wsmysyn

The most common method I have seen is to use CY7C68013A to do LA. You can find it on Taobao, and there is also LA software and LA firmware online.

w494143467

wsmysyn posted on 2020-10-27 20:29 The most common one I have seen is using CY7C68013A to make LA, which is available on Taobao, and there is also LA software and LA firmware on the Internet.

Are there any examples provided? Or do I have to write it from scratch?

shipeng

w494143467 posted on 2020-10-27 08:47 Is all the data transmitted? Or only the valid data? I also bought a logic analyzer and will try it out later.

You taste it, you taste it carefully...

w494143467

shipeng published on 2020-10-28 08:42 Taste it, taste it carefully. . .

I'll try someone else's logic analyzer to see what the principle is, maybe that will give me some ideas.

wsmysyn

w494143467 posted on 2020-10-27 22:05 Are there any examples provided? Or do I have to write it from scratch?

I remember someone posted a DIY LA using 68013 on EE. If you search, you will find that he has worked on it from hardware to software.

https://en.eeworld.com/bbs/thread-1123499-1-1.html

saleae logic

tinnu

w494143467 posted on 2020-10-27 20:09 I checked this development board and it seems that it is not available on Taobao. . .

EBAZ4205 is a mining card FPGA, and the main control is the ZYNQ7010 XILINX FPGA chip, which can only be found on a certain fish. The official development tool has a logic analysis function, which is quite troublesome to be honest, and there is no waveform protocol analysis. For a logic analyzer, unless the demand exceeds 8 channels and 24M, a 30-yuan thing on Taobao is enough. You may not be able to achieve this level if you make it yourself, and even if you can achieve software adaptation, it is still a problem.

tinnu

w494143467 posted on 2020-10-26 22:00 In this case, the development of the host computer is still quite troublesome. Do you have any opinions on the protocol?

There are some open source software for logic analyzer host computers. You can refer to what protocols other host computers accept. It would be best to join other people's ecosystems. In fact, the most troublesome part of the logic analyzer host computer is the analysis part.

w494143467

tinnu posted on 2020-10-28 13:56 There are still some open source software for the logic analyzer host computer. You can refer to what protocol other people's host computers accept. It would be best to join other people's ecosystems. Other...

It is indeed troublesome to make a host computer. I currently want to use QT to make one. After testing it, the transmission rate is acceptable.

w494143467

wsmysyn posted on 2020-10-28 12:30 w494143467 posted on 2020-10-27 22:05 Is there a sample program? Or do I have to write it from scratch? I remember someone posted one on EE...

After taking a look, it seems to be a work in progress.