V58C2512804SEI6 datasheet, PDF

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V58C2512804SEI6: DescriptionDDR DRAM, 64MX8, 0.7ns, CMOS, PDSO66,; Categorystorage storage; File Size1MB，60 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V58C2512804SEI6 Overview

DDR DRAM, 64MX8, 0.7ns, CMOS, PDSO66,

V58C2512804SEI6 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	114797815
package instruction	TSSOP, TSSOP66,.46
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	0.7 ns
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PDSO-G66
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	8
Number of terminals	66
word count	67108864 words
character code	64000000
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP66,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Continuous burst length	2,4,8
Maximum standby current	0.01 A
Maximum slew rate	0.255 mA
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL

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V58C2512(804/164)SE

HIGH PERFORMANCE 512 Mbit DDR SDRAM

4 BANKS X 16Mbit X 8 (804)

4 BANKS X 8Mbit X 16 (164)

PRELIMINARY

DDR500

Clock Cycle Time (t

CK2

)

Clock Cycle Time (t

CK2.5

)

Clock Cycle Time (t

CK3

)

System Frequency (f

CK max

)

4ns

250 MHz

DDR400

7.5ns

6ns

5ns

200 MHz

DDR333

7.5ns

6ns

166 MHz

DDR266

7.5ns

133 MHz

Features

Description

The V58C2512(804/164)SE is a four bank DDR DRAM

organized as 4 banks x 16Mbit x 8 (804), 4 banks x 8Mbit x

16 (164). The V58C2512(804/164)SE achieves high

speed data transfer rates by employing a chip architec-

ture that prefetches multiple bits and then synchronizes

the output data to a system clock.

All of the control, address, circuits are synchronized

with the positive edge of an externally supplied clock. I/O

transactions are occurring on both edges of DQS.

Operating the four memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. A se-

quential and gapless data rate is possible depending on

burst length, CAS latency and speed grade of the device.

High speed data transfer rates with system frequency

up to 250MHz

Data Mask for Write Control

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2, 2.5, 3

Programmable Wrap Sequence: Sequential

or Interleave

Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

Automatic and Controlled Precharge Command

Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 8192 cycles/64 ms

Available in 60 Ball FBGA and 66 Pin TSOP II

SSTL-2 Compatible I/Os

Double Data Rate (DDR)

Bidirectional Data Strobe (DQS) for input and output

data, active on both edges

On-Chip DLL aligns DQ and DQs transitions with CK

transitions

Differential clock inputs CK and CK

Power Supply 2.5V ± 0.2V

tRAS lockout supported

Concurrent auto precharge option is supported

Device Usage Chart

Operating

Temperature

Range

0°C to 70°C

-40°C to 85°C

Package Outline

JEDEC 66 TSOP II

60 FBGA

•

CK Cycle Time (ns)

-4

•

Power

-75

•

-5

•

-6

•

Std.

•

Temperature

Mark

Blank

V58C2512(804/164)SE Rev.1.0 January 2014

V58C2512804SEI6 Related Products

	V58C2512804SEI6	V58C2512804SELI6	V58C2512164SEJ5
Description	DDR DRAM, 64MX8, 0.7ns, CMOS, PDSO66,	DDR DRAM, 64MX8, 0.7ns, CMOS, PDSO66,	DDR DRAM, 32MX16, 0.7ns, CMOS, PBGA60,
Is it Rohs certified?	conform to	conform to	conform to
Objectid	114797815	114797831	114797853
package instruction	TSSOP, TSSOP66,.46	TSSOP, TSSOP66,.46	BGA, BGA60,9X12,40/32
Reach Compliance Code	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
Maximum access time	0.7 ns	0.7 ns	0.7 ns
Maximum clock frequency (fCLK)	166 MHz	166 MHz	200 MHz
I/O type	COMMON	COMMON	COMMON
interleaved burst length	2,4,8	2,4,8	2,4,8
JESD-30 code	R-PDSO-G66	R-PDSO-G66	R-PBGA-B60
memory density	536870912 bit	536870912 bit	536870912 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM
memory width	8	8	16
Number of terminals	66	66	60
word count	67108864 words	67108864 words	33554432 words
character code	64000000	64000000	32000000
Maximum operating temperature	70 °C	70 °C	70 °C
organize	64MX8	64MX8	32MX16
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	BGA
Encapsulate equivalent code	TSSOP66,.46	TSSOP66,.46	BGA60,9X12,40/32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	GRID ARRAY
power supply	2.5 V	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192
Continuous burst length	2,4,8	2,4,8	2,4,8
Maximum standby current	0.01 A	0.01 A	0.01 A
Maximum slew rate	0.255 mA	0.255 mA	0.295 mA
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	BALL
Terminal pitch	0.635 mm	0.635 mm	0.8 mm
Terminal location	DUAL	DUAL	BOTTOM

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