QL1P200-6PS324C datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> QL1P200-6PS324C

QL1P200-6PS324C: DescriptionField Programmable Gate Array, 200MHz, 1536-Cell, CMOS, PBGA324,; CategoryProgrammable logic devices Programmable logic; File Size2MB，96 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

Download Datasheet Parametric Compare View All

QL1P200-6PS324C Overview

Field Programmable Gate Array, 200MHz, 1536-Cell, CMOS, PBGA324,

QL1P200-6PS324C Parametric

Parameter Name	Attribute value
Maker	QuickLogic Corporation
Reach Compliance Code	compli
maximum clock frequency	200 MHz
Number of entries	292
Number of logical units	1536
Output times	292
Number of terminals	324
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA324(UNSPEC)
Package form	GRID ARRAY
power supply	1.8,3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal location	BOTTOM

Preview

Download Datasheet

View All

QuickLogic PolarPro™ Data Sheet

• • • • • •

Combining Low Power, Performance, Density, and Embedded RAM

Device Highlights

Low Power Programmable Logic

• As low as 2.2 µA

• 0.18 µm, six layer metal CMOS process

• 1.8 V core voltage, 1.8/2.5/3.3 V drive

capable I/Os

• Up to 221 kilobits of SRAM

• Up to 292 I/Os available

• Up to one million system gates

• Nonvolatile, instant-on

• IEEE 1149.1 boundary scan testing compliant

4 programmable global clock networks

• Quadrant-based segmentable clock networks

20 quad clock networks per device

4 quad clock networks per quadrant

1 dedicated clock network per quadrant

• Two user Configurable Clock Managers (CCMs)

Very Low Power (VLP) Mode

• QuickLogic PolarPro has a special VLP pin

which can enable a low power sleep mode that

significantly reduces the overall power

consumption of the device by placing the device in

standby.

• Enter VLP mode from normal operation in less

than 250 µs (typical)

• Exit from VLP mode to normal operation in less

than 250 µs (typical)

Embedded Dual-Port SRAM

• Up to twelve dual-port 4-kilobit high performance

SRAM blocks (QL1P075, QL1P100, QL1P200,

and QL1P300 devices)

• Up to twenty-four dual-port 8-kilobit high

performance SRAM blocks (QL1P600 and

QL1P1000 devices)

• Embedded synchronous/asynchronous FIFO

controller

• Configurable and cascadable aspect ratio

Security Links

There are several security links to disable JTAG

access to the device. Programming these optional

links completely disables access to the device from

the outside world and provides an extra level of

design security not possible in SRAM-based FPGAs.

Figure 1: QuickLogic PolarPro Block Diagram

CCM

GPIO

DDR/GPIO

Programmable I/O

• Bank programmable drive strength

• Bank programmable slew rate control

• Independent I/O banks capable of supporting

multiple I/O standards in one device

• Native support for DDR I/Os

• Bank programmable I/O standards: LVTTL,

LVCMOS, and LVCMOS18

CCM

GPIO

Embedded RAM Blocks

FIFO Controller

GPIO

Fabric

GPIO

FIFO Controller

GPIO

Advanced Clock Network

• Multiple low skew clock networks

1 dedicated global clock network

Embedded RAM Blocks

GPIO

www.quicklogic.com

•

QL1P200-6PS324C Related Products

	QL1P200-6PS324C	QL1P200-6PS324I	QL1P200-6PS324M	QL1P200-7PS324C	QL1P200-7PS324I	QL1P200-7PS324M
Description	Field Programmable Gate Array, 200MHz, 1536-Cell, CMOS, PBGA324,	Field Programmable Gate Array, 200MHz, 1536-Cell, CMOS, PBGA324,	Field Programmable Gate Array, 200MHz, 1536-Cell, CMOS, PBGA324,	Field Programmable Gate Array, 200MHz, 1536-Cell, CMOS, PBGA324,	Field Programmable Gate Array, 200MHz, 1536-Cell, CMOS, PBGA324,	Field Programmable Gate Array, 200MHz, 1536-Cell, CMOS, PBGA324,
Maker	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation
Reach Compliance Code	compli	compli	compli	compli	compli	compli
maximum clock frequency	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz
Number of entries	292	292	292	292	292	292
Number of logical units	1536	1536	1536	1536	1536	1536
Output times	292	292	292	292	292	292
Number of terminals	324	324	324	324	324	324
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA324(UNSPEC)	BGA324(UNSPEC)	BGA324(UNSPEC)	BGA324(UNSPEC)	BGA324(UNSPEC)	BGA324(UNSPEC)
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
power supply	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
package instruction	-	-	BGA, BGA324(UNSPEC)	BGA, BGA324(UNSPEC)	BGA, BGA324(UNSPEC)	BGA, BGA324(UNSPEC)

Recommended Resources

Design of voice recording and playback circuit module composed of HY560

CPU and decoding chip memory, SD memory card socket interface circuit

Bathroom exhaust fan automatic control circuit

Inverter circuit design that can eliminate high-order harmonics

40W/8Ω and 60W/4Ω audio power amplifier circuit

What are resonance and resonance? What are their hazards?: What are resonance and resonance? What are their hazards? Tesla said that he could use it to "split the earth in two"?...; aigtekatdz Test/Measurement

About broadband amplifier design: Dear seniors, I am designing a circuit to detect the current. The measurement range is about 10k~200M, and the current is mA level, about 100mA. I would like to ask, how should such a current signal b...; 桂花载酒少年游 RF/Wirelessly

Use MicroPython development board to read and display custom Chinese character library: [i=s]This post was last edited by Walkline on 2021-9-5 00:10[/i]MicroPython New FontLib### Project Introduction Use `MicroPython development board` to read and display custom fonts### Get the complete...; Walkline MicroPython Open Source section

Test LWIP UDP (STM32H750/STM32H743) receiving 5913 and above, it will enter HardFault in about 5 seconds...: When testing LWIP UDP (STM32H750/STM32H743) receiving 5913 and above, it enters the HardFault_Handler crash state in about 5 seconds. Has anyone encountered a similar problem?...; cjq_enjoy ARM Technology

EEWORLD University Hall----Robotics Technology and Applications: Robotics Technology and Applications : https://training.eeworld.com.cn/course/5040In recent years, the robot industry has experienced explosive growth. Whether in the traditional industrial manufactur...; 木犯001号 Industrial Control Electronics

Zhouyi Compass Simulation Experiment 2——Environment and Routine Analysis: Zhouyi Compass Simulation Experiment 2——Environment and Routine Analysis In simulation experiment 1 (https://en.eeworld.com/bbs/thread-1176160-1-1.html), we installed the docker software, loaded and r...; tobot Domestic Chip Exchange

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components