P r o du c t B r i e f
IGLOO
TM
e Low Power Flash FPGAs with
Flash*Freeze
TM
Technology
Features and Benefits
Low Power
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•
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•
•
1.2 V or 1.5 V Core Voltage for Low Power
Supports Single-Voltage System Operation
Low Power Active Capability Enables Active FPGA
Operation with Ultra-Low Power
Flash*Freeze Technology Enables Ultra-Low Power
Consumption While Maintaining FPGA Content
Quick and Easy Way to Enter and Exit Flash*Freeze
Mode Using Flash*Freeze Pin
600 k to 3 Million System Gates
108 k to 504 kbits of True Dual-Port SRAM
Up to 616 User I/Os
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532-
compliant)
FlashLock
®
to Secure FPGA Contents
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
®
Pro (Professional) I/O
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—Up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V/
2.5 V/1.8 V/1.5 V, 3.3 V PCI/ 3.3 V PCI-X, and LVCMOS
2.5 V/5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V/3.3 V,
GTL 2.5 V/3.3 V, HSTL Class I and II, SSTL2 Class I and II,
SSTL3 Class I and II
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay
Schmitt-Trigger Option on Single-Ended Inputs
Weak Pull-Up/Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages Across the IGLOOe Family
Six CCC Blocks, Each with an Integrated PLL
Flexible Phase-Shift, Multiply/Divide, and Delay
Capabilities
Wide Input Frequency Range (1.5 MHz to 200 MHz)
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect Ratio 4,608-Bit
RAM Blocks (x1, x2, x4, x9, and x18 organizations
available)
True Dual-Port SRAM (except x18)
High Capacity
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•
•
•
•
•
•
•
Reprogrammable Flash Technology
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
Embedded Memory
High-Performance Routing Hierarchy
Table 1 •
IGLOOe Product Family
AGLE600
600 k
13,824
60
108
24
1k
Yes
6
18
8
270
FG256, FG484
AGLE3000
3M
75,264
245
504
112
1k
Yes
6
18
8
616
FG484, FG896
IGLOOe Devices
System Gates
VersaTiles (D-Flip-Flops)
Quiescent Current (typical) in Flash*Freeze Mode (µA)
RAM kbits (1,024 bits)
4,608 Bit Blocks
FlashROM Bits
Secure (AES) ISP
CCCs with Integrated PLLs
VersaNet Globals
1
I/O Banks
Maximum User I/Os
Package Pins
FBGA
Notes:
1. Six chip (main) and three quadrant global networks are available.
2. For devices supporting lower densities, refer to the
IGLOO Flash FPGAs
datasheet.
May 2007
© 2007 Actel Corporation
1
See the Actel website for the latest version of the datasheet.
IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology
I/Os Per Package
1
IGLOOe Devices
AGLE600
I/O Types
Package (Dimensions mm)
FG256 (17x17)
FG484 (27x27)
FG896 (31x31)
Notes:
1. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
2. For A3GLE3000 devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
3. FG256 and FG484 are footprint-compatible packages.
4. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (V
REF
) per minibank
(group of I/Os).
5. When the Flash*Freeze pin is used to enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os
available is reduced by 1.
6. "G" indicates RoHS compliant packages. Refer to the
"IGLOOe Ordering Information"
for the location of the "G" in the part
number.
Single-Ended
I/O
1
165
270
–
Differential
I/O Pairs
79
135
–
Single-Ended
I/O
1
–
280
616
Differential
I/O Pairs
–
136
300
AGLE3000
3
IGLOOe Ordering Information
AGLE3000 _
1
FG
G
896
I
Application (Ambient Temperature Range)
Blank =
Commercial
(0˚C to +70˚C)
I = Industrial (–40˚C to +85˚C)
PP = Pre-Production
ES = Engineering
Sample
(Room Temperature Only)
Package Lead
Count
Lead-Free Packaging
Blank =
Standard
Packaging
G
= RoHS
Compliant
(Green) Packaging
Package Type
FG = Fine Pitch Ball
Grid
Array (1.0 mm pitch)
Speed Grade
F = 20%
Slower
than
Standard*
Blank =
Standard
Part Number
IGLOOe Devices
AGLE600 =
600,000 System Gates
AGLE3000 = 3,000,000
System Gates
Note:
*The characteristics provided for –F speed grade are subject to change after establishing FPGA specifications. Some restrictions
might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in commercial
temperature range.
2
P ro du ct B ri e f
IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology
Temperature Grade Offerings
Package
FG256
FG484
FG896
Note:
C = Commercial temperature range: 0°C to 70°C ambient
I = Industrial temperature range: –40°C to 85°C ambient
AGLE600
C, I
C, I
–
AGLE3000
–
C, I
C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
–F
1
✓
–
Std.
✓
✓
Notes:
1. The characteristics provided for –F speed grade are subject to change after establishing FPGA specifications. Some restrictions
might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in commercial
temperature range.
2. C = Commercial temperature range: 0°C to 70°C ambient
3. I = Industrial temperature range: –40°C to 85°C ambient
Contact your local Actel representative for device availability (http://www.actel.com/company/contact/offices/).
P ro du c t B ri ef
3
IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology
Introduction and Overview
General Description
The IGLOOe family of Flash FPGAs, based on a 130-nm
Flash process, offers the lowest power FPGA, a single-
chip
solution,
small
footprint
packages,
reprogrammability, and an abundance of advanced
features.
The Low Power Active capability (static idle) allows for
ultra-low power consumption while the IGLOOe device is
completely functional in the system by maintaining I/O,
SRAM, registers, and logic functions. This allows the
IGLOOe device to control the system power management
based on external inputs (e.g., scanning for keyboard
stimulus) while consuming minimal power.
The Flash*Freeze technology used in IGLOOe devices
allows entering and exiting an ultra-low power mode
while retaining SRAM and register data. Flash*Freeze
technology simplifies power management through I/O
and clock management with rapid recovery to operation
mode.
Nonvolatile Flash technology gives IGLOOe devices the
advantage of being a secure, low power, single-chip
solution that is live at power-up (LAPU). IGLOOe is
reprogrammable and offers time to market benefits at
an ASIC-level unit cost.
These features enable designers to create high-density
systems using existing ASIC or FPGA design flows and
tools.
IGLOOe devices offer 1 kbit of on-chip, programmable,
nonvolatile FlashROM memory storage as well as clock
conditioning circuitry based on 6 integrated phase-
locked loops (PLLs). IGLOOe devices have up to 3 million
system gates, supported with up to 504 kbits of true
dual-port SRAM and up to 616 user I/Os.
Flash*Freeze technology allows the user to keep all power
supplies, I/Os, and clocks connected to the device in normal
operation. When the IGLOOe device enters Flash*Freeze
mode, the device automatically shuts off the clocks and
inputs to the FPGA core; when the device exits Flash*Freeze
mode, all activity resumes and data is retained.
This
low
power
feature,
combined
with
reprogrammability, a single-chip and single-voltage
solution, and availability of small-footprint, high
pin-count packages, makes IGLOOe devices the best fit
for portable electronics.
Flash Advantages
Low Power
Flash-based IGLOOe devices exhibit power characteristics
similar to those of an ASIC, making them an ideal choice
for power-sensitive applications. IGLOOe devices have
only a very limited power-on current surge and no high-
current transition period, both of which occur on many
FPGAs.
IGLOOe devices also have low dynamic power
consumption to further maximize power savings, which
is also reduced by the use of 1.2 V core voltage.
Low dynamic power consumption, combined with low
static power consumption and Flash*Freeze technology,
makes the IGLOOe device the lowest total system power
offered by any FPGA.
Security
The nonvolatile, Flash-based IGLOOe devices do not
require a boot PROM, so there is no vulnerable external
bitstream that can be easily copied. IGLOOe devices
incorporate FlashLock, which provides a unique
combination of reprogrammability and design security
without external overhead, advantages that only an
FPGA with nonvolatile Flash programming can offer.
IGLOOe devices utilize a 128-bit Flash-based lock and a
separate AES key to secure programmed intellectual
property and configuration data. In addition, all
FlashROM data in the IGLOOe devices can be encrypted
prior to loading, using the industry-leading AES-128
(FIPS192) bit block cipher encryption standard. The AES
standard was adopted by the National Institute of
Standards and Technology (NIST) in 2000, and replaces
the 1977 DES standard. IGLOOe devices have a built-in
AES decryption engine and a Flash-based AES key that
make them the most comprehensive programmable logic
Flash*Freeze Technology
The IGLOOe device offers unique Flash*Freeze
technology that allows the IGLOOe device to enter and
exit an ultra-low power mode. IGLOOe devices do not
need additional components to turn off I/Os or clocks
while retaining the design information, SRAM content,
and registers. The Flash*Freeze technology is combined
with in-system programmability, which allows users to
quickly and easily upgrade and update the design in the
final stages of manufacturing or in the field. The ability
of IGLOOe to support 1.2 V core voltage allows further
reduction of power consumption, thus achieving the
lowest total system power.
4
P ro du ct B ri e f
IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology
device security solution available today. IGLOOe devices
with AES-based security allow for secure, remote field
updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of
system overbuilders, system cloners, and IP thieves. The
contents of a programmed IGLOOe device cannot be
read back, although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent
component of the IGLOOe family. The Flash cells are
located beneath seven metal layers, and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. The IGLOOe family,
with FlashLock and AES security, is unique in being highly
resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP
possible. An IGLOOe device provides the most
impenetrable security for programmable logic designs.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost,
performance, and ease of use. Unlike SRAM-based
FPGAs, Flash-based IGLOOe devices allow all
functionality to be live at power-up; no external boot
PROM is required. On-board security mechanisms
prevent access to all the programming information and
enable secure remote updates of the FPGA logic.
Designers can perform secure remote in-system
reprogramming to support future design iterations and
field upgrades with confidence that valuable intellectual
property (IP) cannot be compromised or copied. Secure
ISP can be performed using the industry-standard AES
algorithm. The IGLOOe family device architecture
mitigates the need for ASIC migration at higher user
volumes. This makes the IGLOOe family a cost-effective
ASIC replacement solution, especially for applications in
the consumer, networking/communications, computing,
and avionics markets.
Single Chip
Flash-based FPGAs store the configuration information
in on-chip Flash cells. Once programmed, the
configuration data is an inherent part of the FPGA
structure and no external configuration data needs to be
loaded at system power-up (unlike SRAM-based FPGAs).
Therefore, Flash-based IGLOOe FPGAs do not require
system configuration components such as EEPROMs or
microcontrollers to load the device configuration data.
This reduces bill-of-materials costs and printed circuit
board (PCB) area, and increases security and system
reliability.
Firm Errors
Firm errors occur most commonly when high-energy
neutrons, generated in the upper atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the
collision can change the state of the configuration cell
and thus change the logic, routing, or I/O behavior in an
unpredictable way. These errors are impossible to
prevent in SRAM FPGAs. The consequence of this type of
error can be a complete system failure. Firm errors do
not exist in the configuration memory of IGLOOe Flash-
based FPGAs. Once it is programmed, the Flash cell
configuration element of IGLOOe FPGAs cannot be
altered by high-energy neutrons and is therefore
immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily
be mitigated by using error detection and correction
(EDAC) circuitry built into the FPGA fabric.
Live at Power-Up
The Actel Flash-based IGLOOe devices support Level 0 of
the live at power-up (LAPU) classification standard. This
feature helps in system component initialization,
execution of critical tasks before the processor wakes up,
setup and configuration of memory blocks, clock
generation, and bus activity management. The LAPU
feature of Flash-based IGLOOe devices greatly simplifies
total system design and reduces total system cost, often
eliminating the need for complex programmable logic
devices (CPLDs) and clock generation PLLs that are used
for these purposes in a system. In addition, glitches and
brownouts in system power will not corrupt the IGLOOe
device's Flash configuration, and unlike SRAM-based
FPGAs, the device will not have to be reloaded when
system power is restored. This enables the reduction or
complete removal of the configuration PROM, expensive
voltage monitor, brownout detection, and clock
generator devices from the PCB design. Flash-based
IGLOOe devices simplify total system design, and reduce
cost and design risk, while increasing system reliability
and improving system initialization time.
Advanced Flash Technology
The IGLOOe family offers many benefits, including
nonvolatility and reprogrammability through an
advanced Flash-based, 130-nm LVCMOS process with 7
layers of metal. Standard CMOS design techniques are
used to implement logic and control functions. The
combination of fine granularity, enhanced flexible
routing resources, and abundant Flash switches allows
for very high logic utilization without compromising
device routability or performance. Logic functions within
the device are interconnected through a four-level
routing hierarchy.
P ro du c t B ri ef
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