ISL6244
Multi-Phase PWM Controller
T
O DUC M ENT
T E PR
CE
LE
OB S O D E D R E P L A C e n t e r a t
M ME N
sc
ppor t
RECO echnical Su tersil.com/t
NO
ou r T
ww.in
ontact TERSIL or w
c
IN
1-888-
DATASHEET
FN9106
Rev 3.00
December 28, 2004
The ISL6244 provides core-voltage regulation by driving 2 to
4 interleaved synchronous-rectified buck-converter channels
in parallel. Interleaving the channel timing results in
increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
The ISL6244 uses cost and space-saving r
DS(ON)
sensing
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 100mV using a single external
resistor. The entire system is trimmed to ensure a system
accuracy of ± 1%.
Outstanding features of this controller IC include
Dynamic VID
TM
technology allowing seamless on-the-fly VID
changing without the need of any external components.
Battery “feed-forward” is provided to allow for traditional
control schemes over total input voltage variation. Output
voltage “droop” or active voltage positioning is optional.
When employed, it allows the reduction in size and cost of
the output capacitors required to support load transients. A
threshold-sensitive enable input allows the use of an
external resistor divider for start-up coordination with Intersil
MOSFET drivers or any other devices powered from a
separate supply.
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to reduce the output voltage.
Under-voltage conditions are detected, but PWM operation
is not disrupted. Over-current conditions cause a hiccup-
mode response as the controller repeatedly tries to restart.
After a set number of failed startup attempts, the controller
latches off. A power good logic signal indicates when the
converter output is between the UV and OV thresholds.
Features
• Multi-Phase Power Conversion
- 2, 3 or 4 Phase Operation
• Active Channel Current Balancing
• Precision r
DS(ON)
Current Sharing
- Lossless
- Low Cost
• Precision CORE Voltage Regulation
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
- ±1% System Accuracy
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VID Technology
• Programmable Droop Voltage
• Excellent Dynamic Response
- Combined Input Voltage Feed-Forward and Pulse-by-
Pulse Average Current Mode
• Over Current Protection
• Digital Soft Start
• Threshold Sensitive Enable Input
• High Ripple Frequency (160kHz to 4MHz)
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves PCB
efficiency and has a thinner profile
• Pb-Free Available (RoHS Compliant)
Applications
• AMD Hammer Family Processor Voltage Regulator
• Low Output Voltage, High Current DC-DC Converters
• Voltage Regulator Modules
FN9106 Rev 3.00
December 28, 2004
Page 1 of 25
ISL6244
Absolute Maximum Ratings
Supply Voltage, VCC (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to V
CC
+ 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class II
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
QFN Package (Notes 4, 6). . . . . . . . . .
32
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 100°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
3. For VCC > 5.5V, current must be limited to 25mA.
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. Tolerance does not include the VID offset error or any external component tolerances.
6. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
Shutdown Supply
Operating Conditions: VCC = 5V, T
A
= -10°C to 100°C. Unless Otherwise Specified.
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 5VDC; EN = 5VDC; R
T
= 100k ±1%
VCC = 5VDC; EN = 0VDC; R
T
= 100k±1%
8.0
8.0
10.8
10.3
14.0
13.0
mA
mA
POWER-ON RESET AND ENABLE
POR Threshold
VCC Rising
VCC Falling
ENABLE Threshold
EN Rising
Hysteresis
REFERENCE VOLTAGE AND DAC
System Accuracy (Note 5)
0 to 70°C
VID on Fly Step Size
VID Pull Up
VID Input Low Level
VID Input High Level
PIN-ADJUSTABLE OFFSET
OFS Current
Offset Accuracy
ROFS = 5k±1%
ROFS = 5k±1% , 0 to 70°C
Maximum Offset
OSCILLATOR
Accuracy
RT = 100K
Adjustment Range
VFF Range
Max Duty Cycle
-12.5
245
0.08
0.5
-
-
280
-
-
75
12.5
315
1.0
2.5
-
%
kHz
MHz
V
%
-
92.0
94.0
-
100
100.0
100.0
-
-
108.0
106.0
100.0
mV
A
mV
R
T
= 100k
-1.2
-1
-
-30
-
2.0
-
-
25
-20
-
-
1.2
1
-
-10
0.8
-
%VID
%VID
mV
A
V
V
4.25
3.75
1.215
82
4.35
3.85
1.240
92
4.60
4.00
1.265
102
V
V
V
mV
FN9106 Rev 3.00
December 28, 2004
Page 3 of 25