STB95N4F3, STD95N4F3
STP95N4F3
N-channel 40 V, 5.0 mΩ 80 A STripFET™ III
,
Power MOSFET in D²PAK, DPAK, TO-220
Features
Order codes
STB95N4F3
STD95N4F3
STP95N4F3
■
■
V
DSS
R
DS(on)
max.
< 5.8 m
Ω
< 6.2 mΩ
I
D
Pw
TAB
TAB
40 V
80 A
110 W
3
1
TAB
3
1
3
1
2
Standard threshold drive
100% avalanche tested
D²PAK
DPAK
TO-220
Applications
■
Switching applications
– Automotive
Figure 1.
Internal schematic diagram
Description
These devices are N-channel enhancement mode
Power MOSFETs produced using
STMicroelectronics’ STripFET™ III technology,
which is specifically designed to minimize on-
resistance and gate charge to provide superior
switching performance.
Table 1.
Device summary
Marking
95N4F3
95N4F3
95N4F3
Package
D²PAK
Tape and reel
DPAK
TO-220
Tube
Packaging
Order codes
STB95N4F3
STD95N4F3
STP95N4F3
December 2011
Doc ID 13288 Rev 4
1/20
www.st.com
20
Contents
STB95N4F3, STD95N4F3, STP95N4F3
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
4
5
6
Test circuits
.............................................. 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/20
Doc ID 13288 Rev 4
STB95N4F3, STD95N4F3, STP95N4F3
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
V
DS
V
GS
I
D (1)
I
D
I
DM (2)
P
TOT
dv/dt
(3)
E
AS (4)
T
j
T
stg
Absolute maximum ratings
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Derating factor
Peak diode recovery voltage slope
Single pulse avalanche energy
Operating junction temperature
Storage temperature
Value
40
± 20
80
65
320
110
0.73
8
400
-55 to 175
Unit
V
V
A
A
A
W
W/°C
V/ns
mJ
°C
1. Current limited by package.
2. Pulse width limited by safe operating area.
3. I
SD
≤
80 A, di/dt
≤
400A/µs, V
DS
≤
V
(BR)DSS
, Tj
≤
Tjmax.
4. Starting Tj = 25 °C, I
D
= 40 A, V
DD
= 30 V.
Table 3.
Symbol
R
thj-case
R
thj-a
Thermal resistance
Value
Parameter
D²PAK
Thermal resistance junction-case max
Thermal resistance junction-ambient max
30
50
300
DPAK
1.36
62.5
TO-220
°C/W
°C/W
°C/W
°C
Unit
R
thj-pcb (1)
Thermal resistance junction-ambient max
T
l
Maximum lead temperature for soldering purpose
1. When mounted on 1inch² FR-4 2Oz Cu board.
Doc ID 13288 Rev 4
3/20
Electrical characteristics
STB95N4F3, STD95N4F3, STP95N4F3
2
Electrical characteristics
(T
CASE
=25 °C unless otherwise specified)
Table 4.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Static
Parameter
Drain-source breakdown
voltage
Zero gate voltage drain
current (V
GS
= 0)
Gate body leakage current
(V
DS
= 0)
Gate threshold voltage
Static drain-source on
resistance
Test conditions
I
D
= 250 µA, V
GS
= 0
V
DS
= 40 V,
V
DS
= 40 V,Tc = 125 °C
V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 40 A
V
GS
= 10 V, I
D
= 40 A for TO-220
2
5.0
5.4
Min. Typ. Max. Unit
40
10
100
±
200
V
µA
µA
nA
V
mΩ
mΩ
4
5.8
6.2
Table 5.
Symbol
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
Min. Typ. Max. Unit
2200
580
40
40
11
8
54
pF
pF
pF
nC
nC
nC
V
DS
=25 V, f=1 MHz, V
GS
=0
V
DD
=20 V, I
D
= 80 A
V
GS
=10 V
(see
Figure 14)
-
-
4/20
Doc ID 13288 Rev 4
STB95N4F3, STD95N4F3, STP95N4F3
Electrical characteristics
Table 6.
Symbol
t
d(on)
t
r
t
d(off)
t
f
Switching on/off (inductive load)
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
V
DD
=20 V, I
D
= 40 A,
R
G
=4.7
Ω,
V
GS
=10 V
(see
Figure 16)
V
DD
=20 V, I
D
= 40 A,
R
G
=4.7
Ω,
V
GS
=10 V
(see
Figure 16)
Min.
Typ.
15
50
40
15
Max.
Unit
ns
ns
ns
ns
-
-
-
-
Table 7.
Symbol
I
SD
I
SDM
(1)
Source drain diode
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
=80 A, V
GS
=0
I
SD
=80 A,
di/dt = 100 A/µs,
V
DD
= 30 V, Tj=150 °C
(see
Figure 15)
Test conditions
Min.
-
-
45
60
2.8
Typ.
Max.
80
320
1.5
Unit
A
A
V
ns
nC
A
V
SD (2)
t
rr
Q
rr
I
RRM
-
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Doc ID 13288 Rev 4
5/20
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