512Kx8/256Kx16/128Kx32, 15 - 35ns,
30A167-00
A
Surface Mount
FTE32KX32XP/XHP
1 Megabit CMOS EEPROM
DESCRIPTION:
The FTE32KX32XP/XHP is a high-performance Electrically
Erasable and Programmable Read Only Memory (EEPROM)
module and may be organised as 32K X 32, 64K X 16 or 128K
X 8.
The module is built with four low-power CMOS 32K X 8
EEPROMs. The four chip enables are used for individual
BWDW* selection. The FTE32KX32XP/XHP is ideally suited for
those computer systems having 16-bit or 32-bit architectures.
The FTE32KX32XP/XHP contains a 64-BWDW page register to
allow writing of up to 64 BWDWs simultaneously. During a write
cycle, the address and 1 to 64 BWDWs of data are internally
latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the
module will automatically write the latched data using
an internal control timer. The end of a write cycle can be
detected by DATA Polling of the most significant data bit in
each byte. Once the end of a write cycle has been detected, a
new access for a read or write can begin.
FEATURES:
•
Organisations Available:
32K x 8, 64K x 16 or 128K x 32
•
Access Times: 90ns, 120ns, 150ns
•
Automatic Page Write Operation
•
•
•
•
•
•
Internal Address and Data Latches
Internal Control Timer
Fast Write Cycle Times
Page Write Cycle Time: 10ms maximum
1 to 64 BWDW* Page Write Operation
DATA Polling for END of Write Detection
High Reliability CMOS Technology
Endurance: 10
4
Cycles
Data Retention: 10 years
Single +5V Power Supply, ±10% Tolerance
CMOS and TTL Compatible Inputs and Outputs
Packages Available:
68- “J” Leaded Plastic Surface Mount Module
68- Gull - Leaded Plastic Surface Mount Module
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
Note: Pin 1 Available as WE on request
Rev. 1
1 of 8
March 2014
FTE32KX32XP/XHP
PIN NAMES
A0 - A14
I/O0 - I/O31
CE0 - CE3
WE0 - WE3
OE
V
DD
V
SS
N.C.
Address Inputs
Data Input/Output
Low Chip Enables
Write Enables
Output Enable
Power (+5V)
Ground
No Connect
Load
1
2
C
L
100pF
5pF
OUTPUT LOAD
Parameters Measured
except t
DF
t
DF
RECOMMENDED OPERATING RANGE
1
Symbol
Characteristic
Min. Typ.
Max.
V
DD
4.5 5.0
5.5
Supply Voltage
Input HIGH
V
IH
2.0
Voltage
V
IL
0.8
Input LOW Voltage
-0.5
2
C
0 +25
+70
Operating
T
A
I
-40 +25
+85
Temperature
M
-55 +25 +125
ABSOLUTE MAXIMUM RATINGS
1
Symbol
Parameter
Value
T
STC
-55 to +125
Storage Temperature
Temperature Under
T
BIAS
-55 to +125
Bias
V
DD
-0.6 to +6.25
Supply Voltage
2
V
I/O
-0.6 to +6.25
Input/Output Voltage
2
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output Timing Reference Levels
Unit
V
V
V
o
C
Mode
Standby
Read
Write
Write Inhibit
Write Inhibit
H = HIGH
TRUTH TABLE
CE
OE
H
X
L
L
L
H
X
L
X
X
L = LOW
WE
X
H
L
X
H
I/O Pin
High-Z
D
OUT
D
IN
High-Z
High-Z
X = Don’t Care
Unit
°
C
°C
°C
V
CAPACITANCE
3
:
T
A
= 25
°
C, F = 1.0MHz
Symbol
Parameter
Max. Unit
Condition
C
ADR
Address Input
50
C
CE
15
Chip Enable
pF
V
IN
= 0V
C
WE
15
Write Enable
C
OE
50
Output Enable
C
I/O
20
Data Input/Output
Figure 1. Output Load **
**Including Probe and Jig Capacitance
0V to 3.0V
5ns*
1.5V
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
V
OL
V
OH
V
IL
V
IH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating Supply
Current
V
DD
Standby Supply
Current (CMOS)
Standby Current
(TTL)
Output Low Voltage
Output High Voltage
Input Voltage Low
Input Voltage High
Rev. 1
DC OPERATING CHARACTERISTICS: Over operating ranges
x8
x16
Test Conditions
Min.
Max.
Min.
x32
Min.
Max.
Max.
Unit
mA
mA
mA
mA
mA
V
V
V
V
V
IN
= V
DD
Max
V
OUT
= V
DD
Max
CE = OE= V
IL
all I/O = 0mA, f = 5MHz
CE = V
DD
- 0.3Vdc
CE = V
IH
I
OUT
= 2.1mA
I
OUT
= -400mA
-40
-10
+40
+10
160
12
800
0.45
-40
-20
+40
+20
85
12
800
0.45
-40
-40
+40
+40
50
12
800
0.45
2.4
0.8
2.0
2 of 8
2.4
0.8
2.0
2.4
0.8
2.0
March 2014
FTE32KX32XP/XHP
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
90ns
120ns
150ns
No. Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
t
RC
t
CE
t
ACC
t
OE
t
DF
t
OH
Read Cycle Time
CE to Output Valid
Address Acess Time
Output Enable to Output Valid
Chip Enable or Output enable to Ouput Float
Output Hold from Chip Enable, Output
Enable, or Address, Whichever Occurs First
90
90
90
50
50
0
120
120
120
50
50
0
150
150
150
55
55
0
No.
7
8
9
10
11
12
13
14
15
16
17
18
19
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
:
Over operating ranges
Symbol
Parameter
Min.
Max
t
WC
10
Write Cycle Time
t
AS
0
Address Setup Time
t
AH
50
Address Hold Time
t
CS
0
Chip Select Set-up Time
t
CH
0
Chip Select Hold Time
t
WP
100
Write Pulse Width, (CE or WE)
t
DS
50
Data Set-up Time
t
DH
0
Data Hold Time
t
OES
0
Output Enable Set-up Time
t
OEH
0
Output Enable Hold Time
t
WPH
50
Write Pulse Width High
t
BLC
150
Byte Load Cycle Time
t
WR
0
Write Recovery Time
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
* Valid for both Read and Write Cycles.
READ CYCLE
Rev. 1
3 of 8
March 2014
FTE32KX32XP/XHP
WRITE CYCLE 1: WE Controlled.
WRITE CYCLE 2: CE Controlled
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
NOTES:
1. All voltages are with respect to V
SS
.
2.
Stresses greater than those under
ABSOLUTE
MAXIMUM RATINGS
may cause permanent damage
to the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
Rev. 1
3.
4.
maximum rating conditions for extended periods may
affect reliability
This parameter is guaranteed and not 100% tested.
Address hold time is with respect to the falling
edge of the control signal WE or CE.
5.
WE and CE are noise protected. Less than a 15ns write
pulse will not activate a write cycle.
March 2014
4 of 8
FTE32KX32XP/XHP
PAGE MODE WRITE WAVEFORM
DATA POLLING WAVEFORM
transition is not detected within 150ms of the last low to high transition, the
load period will end and the internal
READ
: The FTE32KX32XP/XHP is accessed like a Static RAM. When
programming period will start. A6 to A14 specify the page address. The
CE and OE are low and WE is high, the data stored at the memory location
page address must be valid during each high to low transition of WE (or
determined by the address pins is asserted on the outputs. The outputs are
CE). A0 to A5 are used to specify which BWDW within the page are to be
put in the high impedance state whenever CE or OE is high. This dual line
written. The BWDWs may loaded in any order and may be changed within
control gives designers flexibility in preventing
the same load period. Only BWDWs which are specified for writing will be
bus contention.
written; unnecessary cycling of other BWDWs within the page does not
WRITE
: A low pulse on the WE or CE input with CE or WE low
occur.
(respectively) and OE high initiates a write cycle. The address is latched on
the falling edge of CE or WE. Once a *BWDW Write has been started it will
DATA POLLING:
Write cycles typically are completed in less time
than the maximum write cycle time of 10ms. To determine when the write
automatically time itself to completion.
is completed, a method called DATA Polling is utilised. If a read is
PAGE WRITE: The page write operation of the FTE32KX32XP/XHP
performed on the address of the last BWDW written to the FTE32KX32XP/XHP
allows 1 to 64 BWDWs of data to be loaded into the device and then
while a write cycle is in progress, the one’s compliment of data most
simultaneously written during the internal programming period. After the
significant bit (I/O7, I/O15, I/O23 and I/O31) will appear on the output.
first data BWDW has been loaded into the device, successive BWDWs may
When the write is completed, a read from the last address written will return
be loaded in the same manner. Each new BWDW to
written must have its high to low transition on WE (or CE) within
150ms
of the
valid data. A DATA Polling may begin at any time during the Write Cycle.
* Byte, Word, or Double Word.
low to high transition of WE (or CE) of the preceding BWDW. If a high to low
DEVICE OPERATION
Rev. 1
5 of 8
March 2014