The CY7C1019D is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight
I/O pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019D is available in standard 32-pin TSOP Type
II and 400-mil-wide SOJ Pb-Free packages.
Logic Block Diagram
Pin Configurations
SOJ /TSOPII
Top View
A
0
A
1
A
2
A
3
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
512 x 256 x 8
ARRAY
I/O
3
I/O
4
I/O
5
CE
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
7
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
16
A
15
A
14
A
13
OE
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
A
12
A
11
A
10
A
9
A
8
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Cypress Semiconductor Corporation
Document #: 38-05464 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 11, 2005
PRELIMINARY
Selection Guide
CY7C1019D-10
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
L
10
60
3
1.2
CY7C1019D
CY7C1019D-12
12
50
3
1.2
Unit
ns
mA
mA
Document #: 38-05464 Rev. *C
Page 2 of 9
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[2]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
[2]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
.................................–0.5V to V
CC
+ 0.5V
CY7C1019D
Current into Outputs (LOW)......................................... 20 mA
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C1019D-10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Test Conditions
Min.
2.4
0.4
2.0
–0.5
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
L
–1
–1
V
CC
+ 0.3
0.8
+1
+1
60
10
10
3.0
L
1.2
2.0
–0.5
–1
–1
Max.
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
7C1019D-12
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
50
10
10
3.0
1.2
mA
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
Automatic CE
Max. V
CC
, CE > V
IH
Power-Down Current V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
—TTL Inputs
Automatic CE
Max. V
CC
,
Power-Down Current CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
—CMOS Inputs
or V
IN
< 0.3V, f = 0
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
6
8
Unit
pF
pF
Thermal Resistance
[3]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
[3]
Thermal Resistance
(Junction to Case)
[3]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
All - Packages
TBD
TBD
Unit
°C/W
°C/W
Notes:
2. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05464 Rev. *C
Page 3 of 9
PRELIMINARY
AC Test Loads and Waveforms
10-ns Devices
OUTPUT
50
Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Equivalent to:
1.5V
Z = 50Ω
12 -ns Devices
5V
CY7C1019D
R1 480Ω
30 pF*
OUTPUT
30 pF
INCLUDING
JIG AND
(b)
SCOPE
High-Z characteristics:
R1 480
Ω
R2
255Ω
(a)
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
ALL INPUT PULSES
3.0V
90%
GND
≤
3 ns
10%
90%
10%
≤
3ns
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(c)
R2
255Ω
Switching Characteristics
Over the Operating Range
[5]
7C1019D-10
Parameter
Read Cycle
t
power[4]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE LOW to Low
Z
[7]
3
5
0
10
10
8
7
0
0
7
5
12
9
8
0
0
8
6
0
12
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
0
5
3
6
3
10
5
0
6
100
10
10
3
12
6
100
12
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C1019D-12
Min.
Max.
Unit
Write Cycle
[8, 9]
Notes:
4. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±200
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05464 Rev. *C
Page 4 of 9
PRELIMINARY
Switching Characteristics
Over the Operating Range (continued)
[5]
7C1019D-10
Parameter
t
HD
t
LZWE
t
HZWE
Description
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
Min.
0
3
5
Max.
0
3
CY7C1019D
7C1019D-12
Min.
Max.
Unit
ns
ns
6
ns
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R[10]
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Non-L, Com’l/Ind’l
L-Version Only
Description
Conditions
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
Min.
2.0
3
1.2
0
t
RC
Max.
Unit
V
mA
mA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
t
CDR
CE
V
DR
> 2V
4.5V
t
R
Switching Waveforms
Read Cycle No. 1
[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[12, 13]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
ISB
ICC
HIGH
IMPEDANCE
Notes:
10. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
µs
or stable at V
CC(min.)
> 50
µs.
11. Device is continuously selected. OE, CE = V
IL
.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.