ICSSSTUA32866BHT datasheet, PDF

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ICSSSTUA32866BHT: DescriptionD Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5.50 X 13.50 MM, MO-205, LFBGA-96; Categorylogic logic; File Size308KB，27 Pages; ManufacturerIDT (Integrated Device Technology)

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ICSSSTUA32866BHT Overview

D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5.50 X 13.50 MM, MO-205, LFBGA-96

ICSSSTUA32866BHT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	LFBGA,
Contacts	96
Reach Compliance Code	not_compliant
series	SSTU
JESD-30 code	R-PBGA-B96
JESD-609 code	e0
length	13.5 mm
Logic integrated circuit type	D FLIP-FLOP
Number of digits	25
Number of functions	1
Number of terminals	96
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	1.9 ns
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	5.5 mm
minfmax	410 MHz

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Integrated

Circuit

Systems, Inc.

ICSSSTUA32866B

25-Bit Configurable Registered Buffer for DDR2

Recommended Application:

•

DDR2 Memory Modules

•

Provides complete DDR DIMM solution with

ICS97ULP877

•

Ideal for DDR2 400,533 and 667

Product Features:

•

25-bit 1:1 or 14-bit 1:2 configurable registered buffer

with parity check functionality

•

Supports SSTL_18 JEDEC specification on data

inputs and outputs

•

Supports LVCMOS switching levels on CSR# and

RESET# inputs

•

Low voltage operation

= 1.7V to 1.9V

•

Available in 96 BGA package

•

Drop-in replacement for ICSSSTUA32864

•

Green packages available

Pin Configuration

Functionality Truth Table

I nputs

RST#

DCS#

X or

Floating

CSR#

X or

Floating

L or H

X or

Floating

L or H

X or

Floating

L or H

CK#

Dn,

DODT,

DCK E

X or

Floating

Outputs

QCS#

QODT,

QCKE

96 Ball BGA

(Top View)

1054A—01/28/05

ICSSSTUA32866BHT Related Products

	ICSSSTUA32866BHT	ICSSSTUA32866BHMLFT	ICSSSTUA32866BHLFT	ICSSSTUA32866BHMT
Description	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5.50 X 13.50 MM, MO-205, LFBGA-96	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 11.50 X 5 MM, LEAD FREE, MO-205,TFBGA-96	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5.50 X 13.50 MM, LEAD FREE, MO-205, LFBGA-96	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 11.50 X 5 MM, MO-205,TFBGA-96
Is it lead-free?	Contains lead	Lead free	Lead free	Contains lead
Is it Rohs certified?	incompatible	conform to	conform to	incompatible
Parts packaging code	BGA	BGA	BGA	BGA
package instruction	LFBGA,	TFBGA,	LFBGA,	11.50 X 5 MM, MO-205,TFBGA-96
Contacts	96	96	96	96
Reach Compliance Code	not_compliant	compliant	compliant	_compli
series	SSTU	SSTU	SSTU	SSTU
JESD-30 code	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96
JESD-609 code	e0	e3	e1	e0
length	13.5 mm	11.5 mm	13.5 mm	11.5 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Number of digits	25	25	25	25
Number of functions	1	1	1	1
Number of terminals	96	96	96	96
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
Output polarity	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	TFBGA	LFBGA	TFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260	260	NOT SPECIFIED
propagation delay (tpd)	1.9 ns	1.9 ns	1.9 ns	1.9 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	1.2 mm	1.5 mm	1.2 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	MATTE TIN	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.65 mm	0.8 mm	0.65 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	30	30	NOT SPECIFIED
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	5.5 mm	5 mm	5.5 mm	5 mm
minfmax	410 MHz	410 MHz	410 MHz	410 MHz
Maker	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)

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