CD4538BCMX_NL datasheet, PDF - EEWORLD Datasheet

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CD4538BCMX_NL: DescriptionMonostable Multivibrator, 4000/14000/40000 Series, 2-Func, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16; Categorylogic logic; File Size135KB，11 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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CD4538BCMX_NL Overview

Monostable Multivibrator, 4000/14000/40000 Series, 2-Func, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16

CD4538BCMX_NL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	SOIC
package instruction	0.150 INCH, MS-012, SOIC-16
Contacts	16
Reach Compliance Code	compliant
series	4000/14000/40000
JESD-30 code	R-PDSO-G16
JESD-609 code	e3
length	9.9 mm
Logic integrated circuit type	MONOSTABLE MULTIVIBRATOR
Humidity sensitivity level	1
Number of data/clock inputs	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	5/15 V
propagation delay (tpd)	0.6 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	15 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm

CD4538BCMX_NL Preview

CD4538BC Dual Precision Monostable

October 1987

Revised April 2002

CD4538BC

Dual Precision Monostable

General Description

The CD4538BC is a dual, precision monostable multivibra-

tor with independent trigger and reset controls. The device

is retriggerable and resettable, and the control inputs are

internally latched. Two trigger inputs are provided to allow

either rising or falling edge triggering. The reset inputs are

active LOW and prevent triggering while active. Precise

control of output pulse-width has been achieved using lin-

ear CMOS techniques. The pulse duration and accuracy

are determined by external components R

and C

. The

device does not allow the timing capacitor to discharge

through the timing pin on power-down condition. For this

reason, no external protection resistor is required in series

with the timing pin. Input protection from static discharge is

provided on all pins.

Features

Wide supply voltage range:

3.0V to 15V

High noise immunity: 0.45 V

(typ.)

Low power TTL compatibility:

Fan out of 2 driving 74L or 1 driving 74LS

New formula:

OUT

RC (PW in seconds, R in Ohms, C in Farads)

1.0% pulse-width variation from part to part (typ.)

Wide pulse-width range:

s to

∞

Separate latched reset inputs

Symmetrical output sink and source capability

Low standby current: 5 nA (typ.) @ 5 V

Pin compatible to CD4528BC

Ordering Code:

Order Number

CD4538BCM

CD4538BCWM

CD4538BCN

Package Number

M16A

M16B

N16E

Package Description

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Inputs

Clear

Outputs

↓

↑

Top View

HIGH Level

LOW Level

↑ =

Transition from LOW-to-HIGH

↓ =

Transition from HIGH-to-LOW

One HIGH Level Pulse

One LOW Level Pulse

Irrelevant

DS006000

www.fairchildsemi.com

CD4538BC

Block Diagram

and C

are External Components

Pin 16

Pin 8

Logic Diagram

FIGURE 1.

www.fairchildsemi.com

CD4538BC

Theory of Operation

FIGURE 2.

Trigger Operation

The block diagram of the CD4538BC is shown in Figure 1,

with circuit operation following.

As shown in Figure 1 and Figure 2, before an input trigger

occurs, the monostable is in the quiescent state with the Q

output low, and the timing capacitor C

completely charged

to V

. When the trigger input A goes from V

to V

(while inputs B and C

are held to V

) a valid trigger is

recognized, which turns on comparator C1 and N-Channel

transistor N1

(1)

. At the same time the output latch is set.

With transistor N1 on, the capacitor C

rapidly discharges

toward V

until V

REF1

is reached. At this point the output

of comparator C1 changes state and transistor N1 turns off.

Comparator C1 then turns off while at the same time com-

parator C2 turns on. With transistor N1 off, the capacitor C

begins to charge through the timing resistor, R

, toward

. When the voltage across C

equals V

REF2

, compara-

tor C2 changes state causing the output latch to reset (Q

goes low) while at the same time disabling comparator C2.

This ends the timing cycle with the monostable in the qui-

escent state, waiting for the next trigger.

A valid trigger is also recognized when trigger input B goes

from V

to V

(while input A is at V

and input C

is at

)

(2)

It should be noted that in the quiescent state C

is fully

charged to V

, causing the current through resistor R

be zero. Both comparators are “off” with the total device

current due only to reverse junction leakages. An added

feature of the CD4538BC is that the output latch is set via

the input trigger without regard to the capacitor voltage.

Thus, propagation delay from trigger to Q is independent of

the value of C

, R

, or the duty cycle of the input wave-

form.

Retrigger Operation

The CD4538BC is retriggered if a valid trigger occurs

(3)

fol-

lowed by another valid trigger

(4)

before the Q output has

returned to the quiescent (zero) state. Any retrigger, after

the timing node voltage at pin 2 or 14 has begun to rise

from V

REF1

, but has not yet reached V

REF2

, will cause an

increase in output pulse width T. When a valid retrigger is

initiated

(4)

, the voltage at T2 will again drop to V

REF1

before

progressing along the RC charging curve toward V

. The

Q output will remain high until time T, after the last valid

retrigger.

Reset Operation

The CD4538BC may be reset during the generation of the

output pulse. In the reset mode of operation, an input pulse

on C

sets the reset latch and causes the capacitor to be

fast charged to V

by turning on transistor Q1

(5)

. When

the voltage on the capacitor reaches V

REF2

, the reset latch

will clear and then be ready to accept another pulse. If the

input is held low, any trigger inputs that occur will be

inhibited and the Q and Q outputs of the output latch will

not change. Since the Q output is reset when an input low

level is detected on the C

input, the output pulse T can be

made significantly shorter than the minimum pulse width

specification.

www.fairchildsemi.com

CD4538BC

FIGURE 3. Retriggerable Monostables Circuitry

FIGURE 4. Non-Retriggerable Monostables Circuitry

FIGURE 5. Connection of Unused Sections

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CD4538BC

Absolute Maximum Ratings

(Note 1)

(Note 2)

DC Supply Voltage (V

)

Input Voltage (V

)

Storage Temperature Range (T

)

Power Dissipation (P

)

Dual-In-Line

Small Outline

Lead Temperature (T

)

(Soldering, 10 seconds)

260

700 mW

500 mW

Recommended Operating

Conditions

(Note 2)

DC Supply Voltage (V

)

Input Voltage (V

)

Operating Temperature Range (T

)

3 to 15 V

0 to V

−

0.5 to

18 V

−

0.5V to V

0.5 V

−

C to

150

−

C to

125

Note 1:

“Absolute Maximum Ratings” are those values beyond which the

safety of the device cannot be guaranteed, they are not meant to imply that

the devices should be operated at these limits. The tables of “Recom-

mended Operating Conditions” and “Electrical Characteristics” provide con-

ditions for actual device operation.

Note 2:

0V unless otherwise specified.

DC Electrical Characteristics

(Note 2)

Symbol

Parameter

Quiescent

Device Current

LOW Level

Output Voltage

HIGH Level

Output Voltage

LOW Level

Input Voltage

10V

15V

10V

15V

10V

15V

µA

5V, V

0.5V or 4.5V

10V, V

1.0V or 9.0V

15V, V

1.5V or 13.5V

HIGH Level

Input Voltage

µA

5V, V

0.5V or 4.5V

10V, V

1.0V or 9.0V

15V, V

1.5V or 13.5V

LOW Level

Output Current

(Note 3)

HIGH Level

Output Current

(Note 3)

Input Current,

Pin 2 or 14

Input Current

Other Inputs

Note 3:

and I

are tested one output at a time.

Conditions

All Outputs Open

µA

, V

µA

, V

−55°C

Min

Max

0.05

4.95

9.95

14.95

1.5

3.0

4.0

3.5

7.0

11.0

0.64

1.6

4.2

−0.6

−1.6

−4.2

±0.02

±0.1

3.5

7.0

11.0

0.51

1.3

3.4

−0.51

−1.3

−3.4

4.95

9.95

14.95

Min

+25°C

Typ

0.005

0.010

0.015

2.25

4.50

6.75

2.75

5.50

8.25

0.88

2.25

8.8

−0.88

−2.25

−8.8

±10

−

±10

−

±0.05

±0.1

1.5

3.0

4.0

Max

0.05

+125°C

Min

Max

150

300

600

0.05

4.95

9.95

14.95

1.5

3.0

4.0

3.5

7.0

11.0

0.36

0.9

2.4

−0.36

−0.9

−2.4

±0.5

±1.0

Units

µA

5V, V

0.4V

10V, V

0.5V

15V, V

1.5V

5V, V

4.6V

10V, V

9.5V

15V, V

13.5V

µA

15V, V

0V or 15V

15V, V

0V or 15V

www.fairchildsemi.com

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