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PE3320B-FREQ

Description
PECL Output Clock Oscillator, 1.5MHz Min, 250MHz Max, LEADLESS PACKAGE-6
CategoryPassive components    oscillator   
File Size71KB,4 Pages
ManufacturerPletronics
Download Datasheet Parametric View All

PE3320B-FREQ Overview

PECL Output Clock Oscillator, 1.5MHz Min, 250MHz Max, LEADLESS PACKAGE-6

PE3320B-FREQ Parametric

Parameter NameAttribute value
MakerPletronics
Reach Compliance Codeunknown
Other featuresTAPE; TUBE; OUTPUT ENABLE/DISABLE FUNCTION
maximum descent time1 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
Manufacturer's serial numberPE3320B
Installation featuresSURFACE MOUNT
Maximum operating frequency250 MHz
Minimum operating frequency1.5 MHz
Maximum operating temperature80 °C
Minimum operating temperature
Oscillator typePECL
physical size14.23mm x 10.16mm x 3.17mm
longest rise time1 ns
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry45/55 %
Pl tronics, Inc.
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
Differential PECL Series
Differential PECL Output, Some with Enable/ Disable Function
Available in 9 Different Package/Configurations, See Next Pages
Standard Specifications
Overall Frequency Stability
Operating Temperature Range
Storage Temperature Range
Supply Voltage (Vcc)
Supply Current (Icc)
Output High Level
± 50 PPM, ± 25 PPM, ± 20 PPM over Operating Temperature Range
0 to +80°C is standard, but can be extended to - 40 to +85°C
- 55 to +125°C
3.3 volts ± 5% standard, but 5.0 volts or 2.5 volts also available. See Test Cirucit 5.
< 250 MHz = 90 mA maximum, 250 MHz and above = 100 mA maximum
2.275 V minimum referenced to Ground, Vcc = 3.300V,
0.975 V minimum referenced to termination voltage,
- 1.025 V minimum referenced to Vcc
1.680 V maximum referenced to Ground, Vcc = 3.300V,
0.380 V maximum referenced to termination voltage,
- 1.620 V maximum referenced to Vcc
45/55% referenced to 50% of amplitude
1.0 nS maximum when Vth is 10% and 90% of waveform
1 pS RMS maximum measured
from 12 kHz to 20 MHz from Fnominal
50 kohm minimum to Vcc
0.3 Vcc maximum referenced to Ground
0.7 Vcc minumum referenced to Ground
Output Low Level
Output Symmetry
Output Rise & Fall (Tr & Tf)
Jitter
E/D Internal Pullup
V disable
V enable
PE7745D only Output Enable / Disable
High Level Input Current
-20 uA maximum at Enable / Disable Pin = 0.7 Vcc
Low Level Input Current
-200 uA maximum at Enable / Disable Pin = 0 V
Output Enable Time
200 nS maximum at output enable or 1 mS maximum at output enabled and stable
Output Disable Time
200 nS maximum at output disable
Vcc Supply Current disabled < 1 mA. Both outputs are high impedance when disabled.
All other models Output Enable/Disable (E/D)
Output Enable Time
100 nS maximum
Output Disable Time
100 nS maximum
When Disabled
Q Output = Logic Low, QN Output = Logic High. Both Outputs are active
Note 1:
PECL and ECL are identical circuits.
ECL has the most positive pin as ground and is ideally terminated by 50 ohms to - 2.00 V
PECL has the most negative pin as ground and is ideally terminated by 50 ohms to the most (positive voltage less 2.00 V)
Mechanical: See Next Pages
D Package
J Package Replacement
B Package
M Package
Mar 2004
Pl tronics, Inc.
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
1
PECL, LVDS, OCXO
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