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IDT74FCTL2841ATQ

Description
Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, QSOP-24
Categorylogic    logic   
File Size86KB,6 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

IDT74FCTL2841ATQ Overview

Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, QSOP-24

IDT74FCTL2841ATQ Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSOIC
package instructionSSOP, SSOP24,.24
Contacts24
Reach Compliance Codenot_compliant
seriesFCT
JESD-30 codeR-PDSO-G24
JESD-609 codee0
length8.65 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.012 A
Humidity sensitivity level1
Number of digits10
Number of functions1
Number of ports2
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE WITH SERIES RESISTOR
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP24,.24
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)225
power supply5 V
Prop。Delay @ Nom-Sup9.5 ns
propagation delay (tpd)20 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.9116 mm

IDT74FCTL2841ATQ Preview

IDT74FCTL2841T
HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
HIGH-SPEED CMOS
BUS INTERFACE
10-BIT LATCH
FEATURES:
Pin and function compatible to the Quality QS74FCT Family
Extended commercial range of –40°C to +85°C
CMOS power levels: <7.5mW static
Available in PDIP, SOIC, and QSOP packages
Undershoot clamp diodes on all inputs
True TTL input and output compatibility
Ground bounce controlled outputs
Reduced output swing of 0 to 3.5V
Built-in 25Ω series resistor outputs reduce reflection and other
system noise
A, B, and C speed grades with 5.5ns t
PD
for C
I
OL
= 12mA
IDT74FCTL2841T
DESCRIPTION:
The IDT74FCTL2841T is a 10-bit high-speed CMOS TTL-compatible
buffered latch with 3-state outputs, ideal for driving high-capacitance loads
such as memory address and data buses. The device comes in A, B, and
C speed grades with 5.5ns (Max.) t
PHL
/t
PLH
for the C grade. The 2841 device
is a 25Ω resistor output version, useful for driving transmission lines and
reducing system noise. The 2841 eliminates the need for external series
resistors in high speed systems and can replace the 841 series to reduce
noise in an existing design. All inputs have clamp diodes for undershoot
noise suppression. All outputs have ground bounce suppression. Outputs
will not load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
25
Di
LE
OE
D
LE
Q
Yi
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
SEPTEMBER 1999
DSC-5260/-
IDT74FCTL2841T
HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
24
23
22
21
20
P24-1
SO24-2
SO24-8
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM(2)
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current (per pin)
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
(1)
Unit
V
V
°C
mA
mA
mA
Max.
– 0.5 to +7
– 0.5 to +7
– 65 to +150
120
– 20
– 50
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GN D
1
2
3
4
5
6
7
8
9
10
11
12
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
LE
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
19
18
17
16
15
14
13
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
FCTL
PDIP/ SOIC/ QSOP
TOP VIEW
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Name
D
I
LE
I/O
I
I
Description
The latch data inputs.
The latch enable input. The latches are transparent
when LE is HIGH. Input data is latched on the HIGH-
to-LOW transition.
The 3-state latch outputs.
The output enable control. When
OE
is LOW, the
outputs are enabled. When
OE
is HIGH, the outputs
VI are in high-impedance (off) state.
FUNCTION TABLE
Inputs
LE
H
H
L
H
H
L
(1)
OE
H
H
H
L
L
L
D
I
L
H
X
L
H
X
Internal
Q
I
L
H
NC
L
H
NC
Output
Y
I
Z
Z
Z
L
H
NC
Function
High Z
High Z
Latched (High Z)
Transparent
Transparent
Latched
Y
I
OE
O
I
LOGIC SYMBOL
Di
10
D
LE
Q
10
NOTE:
1. H = HIGH
L = LOW
X = Don't Care
NC = No Change
Z = High-Impedance
Yi
LE
OE
2
IDT74FCTL2841T
HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Extended Commercial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
V
IH
V
IL
∆V
T
I
IH
I
IL
I
OZ
I
OR
V
IC
V
OH
V
OL
R
OUT
Parameter
Input HIGH Level
Input LOW Level
Input Hysteresis
Input HIGH Current
Input LOW Current
Off-State Output Current (Hi-Z)
Current Drive
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage - 25Ω
Output Resistance - 25Ω
V
CC
= Max.
V
CC
= Min., V
OUT
= 2.0V
(2, 3)
V
CC
= Min., I
IN
= –18mA, T
A
= 25
°
C
(3)
V
CC
= Min.
V
CC
= Min.
V
CC
= Min.
I
OH
= -15mA
I
OL
= 12mA
I
OL
= 12mA
0
V
IN
Vcc
50
2.4
20
–0.7
28
5
–1.2
0.5
40
µA
mA
V
V
V
Test Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
TLH
- V
THL
for all inputs
V
CC
= Max.
0
V
IN
< Vcc
Min.
2.0
Typ.
(1)
0.2
Max.
0.8
5
Unit
V
V
V
µA
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25°C.
2. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
3. This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
Extended Commercial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
I
CC
Parameter
Quiescent Power Supply Current
Test Conditions
(1)
V
CC
= Max.
freq = 0
0V
V
IN
0.2V or
Vcc-0.2V
V
IN
Vcc
V
CC
= Max.
V
IN
= 3.4V
(2)
freq = 0
V
CC
= Max.
Outputs Open and Enabled
One Bit Toggling
50% Duty Cycle
Other inputs at GND or Vcc
(3,4)
Min.
Max.
1.5
Unit
mA
∆I
CC
Supply Current per Input TTL Inputs HIGH
2
mA
I
CCD
Supply Current per Input per MHz
0.25
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven input (V
IN
= 3.4V).
3. For flip-flops, Q
CCD
is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of
device power consumption only and does not include power to drive load capacitance or tester capacitance.
4. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
3
IDT74FCTL2841T
HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
Following Conditions Apply Unless Otherwise Specified:
Extended Commercial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
74FCTL2841AT
Symbol
t
PHL
t
PLH
t
PHL
t
PLH
t
SU
t
H
t
LEY
t
LEY
t
W
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
Parameter
(2)
Data to Y Delay
OE
= LOW
Data to Y Delay
(3,4)
OE
= LOW
Data to LE Setup
Data to LE Hold Time
LE to Y Delay
OE
= LOW
LE to Y Delay
(3,4)
OE
= LOW
LE Pulse Width, HIGH
(3)
Output Enable Time
OE
to Yi
Output Enable Time
(3,4)
OE
to Yi
Output Disable Time
(3,5)
OE
to Yi
Output Disable Time
(3)
OE
to Yi
Min.
2.5
2.5
6
Max.
9.5
20
12
16
11.5
23
7
8
74FCTL2841BT
Min.
2.5
2.5
4
Max.
6.5
13
8
15.5
8
14
6
7
74FCTL2841CT
Min.
2.5
2.5
4
Max.
5.5
13
8
15
6.5
12
5.7
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
2. See Test Circuits and Waveforms.
3. This parameter is guaranteed by design but not tested.
4. C
LOAD
= 300pF
5. C
LOAD
= 5pF
4
IDT74FCTL2841T
HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
V
IN
Pulse
Generator
D.U.T.
50pF
R
T
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Open
FCTL
7.0V
Switch
Closed
V
OUT
500
C
L
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
O ctal lin k
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
t
SU
TIM ING
INPUT
ASYNCHRONOUS C ONTROL
PRES ET
CLEAR
ETC.
SYNCHRO NOUS CONTRO L
PRES ET
CLEAR
CLOCK ENABLE
ETC.
t
REM
t
H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
O ctal lin k
PULSE WIDTH
LO W -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
O ctal lin k
1.5V
1.5V
t
SU
t
H
PROPAGATION DELAY
SAM E PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE P HASE
INPUT TRANSITION
t
PH L
t
PH L
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
O ctal lin k
ENABLE AND DISABLE TIMES
ENAB LE
DISA BLE
3V
CO NTROL
INPUT
t
PZL
OUTPUT
NO RM A LLY
LO W
SW ITCH
CLOSE D
t
PZH
OUTPUT
NO RM A LLY
HIGH
SW ITCH
OPEN
3.5V
1.5V
0.3V
t
PHZ
0.3V
1.5V
0V
0V
O ctal lin k
1.5V
t
PLZ
0V
3.5V
V
OL
V
OH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns
5

IDT74FCTL2841ATQ Related Products

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Description Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, QSOP-24 Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, QSOP-24 Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDIP24, PLASTIC, DIP-24 Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, SOIC-24 Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDIP24, PLASTIC, DIP-24 Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, QSOP-24 Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, SOIC-24
Is it lead-free? Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code SOIC SOIC DIP SOIC DIP SOIC SOIC
package instruction SSOP, SSOP24,.24 SSOP, SSOP24,.24 DIP, DIP24,.3 SOP, SOP24,.4 DIP, DIP24,.3 SSOP, SSOP24,.24 SOP, SOP24,.4
Contacts 24 24 24 24 24 24 24
Reach Compliance Code not_compliant not_compliant not_compliant not_compliant not_compliant not_compliant not_compliant
series FCT FCT FCT FCT FCT FCT FCT
JESD-30 code R-PDSO-G24 R-PDSO-G24 R-PDIP-T24 R-PDSO-G24 R-PDIP-T24 R-PDSO-G24 R-PDSO-G24
JESD-609 code e0 e0 e0 e0 e0 e0 e0
length 8.65 mm 8.65 mm 31.75 mm 15.4 mm 31.75 mm 8.65 mm 15.4 mm
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER
MaximumI(ol) 0.012 A 0.012 A 0.012 A 0.012 A 0.012 A 0.012 A 0.012 A
Number of digits 10 10 10 10 10 10 10
Number of functions 1 1 1 1 1 1 1
Number of ports 2 2 2 2 2 2 2
Number of terminals 24 24 24 24 24 24 24
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Output characteristics 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR
Output polarity TRUE TRUE TRUE TRUE TRUE TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SSOP SSOP DIP SOP DIP SSOP SOP
Encapsulate equivalent code SSOP24,.24 SSOP24,.24 DIP24,.3 SOP24,.4 DIP24,.3 SSOP24,.24 SOP24,.4
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH IN-LINE SMALL OUTLINE IN-LINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE
Peak Reflow Temperature (Celsius) 225 225 225 225 225 225 225
power supply 5 V 5 V 5 V 5 V 5 V 5 V 5 V
Prop。Delay @ Nom-Sup 9.5 ns 6.5 ns 5.5 ns 5.5 ns 6.5 ns 5.5 ns 6.5 ns
propagation delay (tpd) 20 ns 13 ns 13 ns 13 ns 13 ns 13 ns 13 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.75 mm 1.75 mm 4.191 mm 2.65 mm 4.191 mm 1.75 mm 2.65 mm
Maximum supply voltage (Vsup) 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V
Minimum supply voltage (Vsup) 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES NO YES NO YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn/Pb) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING THROUGH-HOLE GULL WING THROUGH-HOLE GULL WING GULL WING
Terminal pitch 0.635 mm 0.635 mm 2.54 mm 1.27 mm 2.54 mm 0.635 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30 30 30 30 30
width 3.9116 mm 3.9116 mm 7.62 mm 7.5 mm 7.62 mm 3.9116 mm 7.5 mm
Humidity sensitivity level 1 1 - 1 - 1 1
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