IDT74FCTL2841CTP datasheet, PDF

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IDT74FCTL2841CTP: DescriptionBus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDIP24, PLASTIC, DIP-24; Categorylogic logic; File Size86KB，6 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT74FCTL2841CTP Overview

Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDIP24, PLASTIC, DIP-24

IDT74FCTL2841CTP Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	DIP
package instruction	DIP, DIP24,.3
Contacts	24
Reach Compliance Code	not_compliant
series	FCT
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
length	31.75 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.012 A
Number of digits	10
Number of functions	1
Number of ports	2
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE WITH SERIES RESISTOR
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Prop。Delay @ Nom-Sup	5.5 ns
propagation delay (tpd)	13 ns
Certification status	Not Qualified
Maximum seat height	4.191 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.62 mm

IDT74FCTL2841CTP Preview

IDT74FCTL2841T

HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH

EXTENDED COMMERCIAL TEMPERATURE RANGE

HIGH-SPEED CMOS

BUS INTERFACE

10-BIT LATCH

FEATURES:

−

Pin and function compatible to the Quality QS74FCT Family

Extended commercial range of –40°C to +85°C

CMOS power levels: <7.5mW static

Available in PDIP, SOIC, and QSOP packages

Undershoot clamp diodes on all inputs

True TTL input and output compatibility

Ground bounce controlled outputs

Reduced output swing of 0 to 3.5V

Built-in 25Ω series resistor outputs reduce reflection and other

system noise

A, B, and C speed grades with 5.5ns t

for C

= 12mA

IDT74FCTL2841T

DESCRIPTION:

The IDT74FCTL2841T is a 10-bit high-speed CMOS TTL-compatible

buffered latch with 3-state outputs, ideal for driving high-capacitance loads

such as memory address and data buses. The device comes in A, B, and

C speed grades with 5.5ns (Max.) t

PHL

PLH

for the C grade. The 2841 device

is a 25Ω resistor output version, useful for driving transmission lines and

reducing system noise. The 2841 eliminates the need for external series

resistors in high speed systems and can replace the 841 series to reduce

noise in an existing design. All inputs have clamp diodes for undershoot

noise suppression. All outputs have ground bounce suppression. Outputs

will not load an active bus when Vcc is removed from the device.

FUNCTIONAL BLOCK DIAGRAM

Ω

EXTENDED COMMERCIAL TEMPERATURE RANGE

1999 Integrated Device Technology, Inc.

SEPTEMBER 1999

DSC-5260/-

IDT74FCTL2841T

HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH

EXTENDED COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION

P24-1

SO24-2

SO24-8

ABSOLUTE MAXIMUM RATINGS

Symbol

TERM(2)

Description

Terminal Voltage with Respect to GND

Storage Temperature

DC Output Current (per pin)

Continuous Clamp Current,

< 0 or V

< 0

(1)

Unit

°C

Max.

– 0.5 to +7

– 65 to +150

120

– 20

– 50

GN D

TERM(3)

STG

OUT

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

2. V

terminals.

3. All terminals except V

CAPACITANCE

= +25

C, f = 1.0MHz)

Symbol

OUT

Parameter

(1)

Input Capacitance

Output Capacitance

Conditions

= 0V

OUT

= 0V

Typ.

Max.

Unit

FCTL

PDIP/ SOIC/ QSOP

TOP VIEW

NOTE:

1. This parameter is measured at characterization but not tested.

PIN DESCRIPTION

Name

I/O

Description

The latch data inputs.

The latch enable input. The latches are transparent

when LE is HIGH. Input data is latched on the HIGH-

to-LOW transition.

The 3-state latch outputs.

The output enable control. When

is LOW, the

outputs are enabled. When

is HIGH, the outputs

VI are in high-impedance (off) state.

FUNCTION TABLE

Inputs

(1)

Internal

Output

Function

High Z

Latched (High Z)

Transparent

Latched

LOGIC SYMBOL

NOTE:

1. H = HIGH

L = LOW

X = Don't Care

NC = No Change

Z = High-Impedance

IDT74FCTL2841T

HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH

EXTENDED COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Extended Commercial: T

= -40°C to +85°C, V

= 5.0V ± 5%

Symbol

∆V

OUT

Parameter

Input HIGH Level

Input LOW Level

Input Hysteresis

Input HIGH Current

Input LOW Current

Off-State Output Current (Hi-Z)

Current Drive

Input Clamp Voltage

Output HIGH Voltage

Output LOW Voltage - 25Ω

Output Resistance - 25Ω

= Max.

= Min., V

OUT

= 2.0V

(2, 3)

= Min., I

= –18mA, T

= 25

(3)

= Min.

= -15mA

= 12mA

≤

Vcc

—

2.4

—

–0.7

—

–1.2

—

0.5

µA

Ω

Test Conditions

Guaranteed Logic HIGH Level

Guaranteed Logic LOW Level

TLH

- V

THL

for all inputs

= Max.

≤

< Vcc

Min.

2.0

—

Typ.

(1)

—

0.2

—

Max.

—

0.8

—

Unit

µA

NOTES:

1. Typical values are at V

= 5.0V, T

= 25°C.

2. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

3. This parameter is guaranteed but not tested.

POWER SUPPLY CHARACTERISTICS

Following Conditions Apply Unless Otherwise Specified:

Extended Commercial: T

= -40°C to +85°C, V

= 5.0V ± 5%

Symbol

Parameter

Quiescent Power Supply Current

Test Conditions

(1)

= Max.

freq = 0

≤

0.2V or

Vcc-0.2V

≤

Vcc

= Max.

= 3.4V

(2)

freq = 0

= Max.

Outputs Open and Enabled

One Bit Toggling

50% Duty Cycle

Other inputs at GND or Vcc

(3,4)

Min.

—

Max.

1.5

Unit

∆I

Supply Current per Input TTL Inputs HIGH

—

CCD

Supply Current per Input per MHz

—

0.25

mA/MHz

NOTES:

1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.

2. Per TLL driven input (V

= 3.4V).

3. For flip-flops, Q

CCD

is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of

device power consumption only and does not include power to drive load capacitance or tester capacitance.

4. I

= I

QUIESCENT

+ I

INPUTS

+ I

DYNAMIC

= I

∆I

+ I

CCD

/2 + f

)

= Quiescent Current

∆I

= Power Supply Current for a TTL High Input (V

= 3.4V)

= Duty Cycle for TTL Inputs High

= Number of TTL Inputs at D

CCD

= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)

= Clock Frequency for Register Devices (Zero for Non-Register Devices)

= Input Frequency

= Number of Inputs at f

All currents are in milliamps and all frequencies are in megahertz.

IDT74FCTL2841T

HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH

EXTENDED COMMERCIAL TEMPERATURE RANGE

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

(1)

Following Conditions Apply Unless Otherwise Specified:

Extended Commercial: T

= -40°C to +85°C, V

= 5.0V ± 5%

74FCTL2841AT

Symbol

PHL

PLH

PHL

PLH

LEY

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

Parameter

(2)

Data to Y Delay

= LOW

Data to Y Delay

(3,4)

= LOW

Data to LE Setup

Data to LE Hold Time

LE to Y Delay

= LOW

LE to Y Delay

(3,4)

= LOW

LE Pulse Width, HIGH

(3)

Output Enable Time

to Yi

Output Enable Time

(3,4)

to Yi

Output Disable Time

(3,5)

to Yi

Output Disable Time

(3)

to Yi

Min.

—

2.5

—

Max.

9.5

—

11.5

74FCTL2841BT

Min.

—

2.5

—

Max.

6.5

—

15.5

—

74FCTL2841CT

Min.

—

2.5

—

Max.

5.5

—

6.5

5.7

Unit

NOTES:

1. C

LOAD

= 50pF, R

LOAD

= 500Ω unless otherwise noted.

2. See Test Circuits and Waveforms.

3. This parameter is guaranteed by design but not tested.

4. C

LOAD

= 300pF

5. C

LOAD

= 5pF

IDT74FCTL2841T

HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH

EXTENDED COMMERCIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

500

Ω

Pulse

Generator

D.U.T.

50pF

SWITCH POSITION

Test

Open Drain

Disable Low

Enable Low

All Other Tests

Open

FCTL

7.0V

Switch

Closed

OUT

500

Ω

DEFINITIONS:

= Load capacitance: includes jig and probe capacitance.

= Termination resistance: should be equal to Z

OUT

of the Pulse

Generator.

O ctal lin k

SET-UP, HOLD, AND RELEASE TIMES

DATA

INPUT

TIM ING

INPUT

ASYNCHRONOUS C ONTROL

PRES ET

CLEAR

ETC.

SYNCHRO NOUS CONTRO L

PRES ET

CLEAR

CLOCK ENABLE

ETC.

REM

1.5V

O ctal lin k

PULSE WIDTH

LO W -HIGH-LOW

PULSE

HIGH-LOW -HIGH

PULSE

O ctal lin k

1.5V

PROPAGATION DELAY

SAM E PHASE

INPUT TRANSITION

PLH

OUTPUT

PLH

OPPOSITE P HASE

INPUT TRANSITION

PH L

1.5V

O ctal lin k

ENABLE AND DISABLE TIMES

ENAB LE

DISA BLE

CO NTROL

INPUT

PZL

OUTPUT

NO RM A LLY

LO W

SW ITCH

CLOSE D

PZH

OUTPUT

NO RM A LLY

HIGH

SW ITCH

OPEN

3.5V

1.5V

0.3V

PHZ

0.3V

1.5V

O ctal lin k

1.5V

PLZ

3.5V

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-

HIGH

2. Pulse Generator for All Pulses: Rate

≤

1.0MHz; t

≤

2.5ns; t

≤

2.5ns

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IDT74FCTL2841CTP Related Products

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Description	Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDIP24, PLASTIC, DIP-24	Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, QSOP-24	Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, QSOP-24	Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, SOIC-24	Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDIP24, PLASTIC, DIP-24	Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, QSOP-24	Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, SOIC-24
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	DIP	SOIC	SOIC	SOIC	DIP	SOIC	SOIC
package instruction	DIP, DIP24,.3	SSOP, SSOP24,.24	SSOP, SSOP24,.24	SOP, SOP24,.4	DIP, DIP24,.3	SSOP, SSOP24,.24	SOP, SOP24,.4
Contacts	24	24	24	24	24	24	24
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
series	FCT	FCT	FCT	FCT	FCT	FCT	FCT
JESD-30 code	R-PDIP-T24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDIP-T24	R-PDSO-G24	R-PDSO-G24
JESD-609 code	e0	e0	e0	e0	e0	e0	e0
length	31.75 mm	8.65 mm	8.65 mm	15.4 mm	31.75 mm	8.65 mm	15.4 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
MaximumI(ol)	0.012 A	0.012 A	0.012 A	0.012 A	0.012 A	0.012 A	0.012 A
Number of digits	10	10	10	10	10	10	10
Number of functions	1	1	1	1	1	1	1
Number of ports	2	2	2	2	2	2	2
Number of terminals	24	24	24	24	24	24	24
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	SSOP	SSOP	SOP	DIP	SSOP	SOP
Encapsulate equivalent code	DIP24,.3	SSOP24,.24	SSOP24,.24	SOP24,.4	DIP24,.3	SSOP24,.24	SOP24,.4
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	IN-LINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	225	225	225	225	225	225	225
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Prop。Delay @ Nom-Sup	5.5 ns	9.5 ns	6.5 ns	5.5 ns	6.5 ns	5.5 ns	6.5 ns
propagation delay (tpd)	13 ns	20 ns	13 ns	13 ns	13 ns	13 ns	13 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.191 mm	1.75 mm	1.75 mm	2.65 mm	4.191 mm	1.75 mm	2.65 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	YES	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	GULL WING	GULL WING	GULL WING	THROUGH-HOLE	GULL WING	GULL WING
Terminal pitch	2.54 mm	0.635 mm	0.635 mm	1.27 mm	2.54 mm	0.635 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30	30	30
width	7.62 mm	3.9116 mm	3.9116 mm	7.5 mm	7.62 mm	3.9116 mm	7.5 mm
Humidity sensitivity level	-	1	1	1	-	1	1

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