TSPC603RCA8LC datasheet, PDF - EEWORLD Datasheet

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TSPC603RCA8LC: DescriptionRISC Microprocessor, 32-Bit, 200MHz, CMOS, CQFP240, CERQUAD-240; CategoryThe embedded processor and controller Microcontrollers and processors; File Size671KB，40 Pages; ManufacturerThales Group

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TSPC603RCA8LC Overview

RISC Microprocessor, 32-Bit, 200MHz, CMOS, CQFP240, CERQUAD-240

TSPC603RCA8LC Parametric

Parameter Name	Attribute value
Maker	Thales Group
Parts packaging code	QFP
package instruction	,
Contacts	240
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	66.7 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-GQFP-G240
low power mode	YES
Number of terminals	240
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, GLASS-SEALED
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
speed	200 MHz
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal location	QUAD
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Features

5.6 SPECint95, 4.0 SPECfp95 @ 200 MHz (estimated)

Superscalar (3 instructions per clock peak).

Dual 16KB caches.

Selectable bus clock.

32-bit compatibility PowerPC implementation.

On chip debug support.

typical = 2.5 Watts (200 MHz), full operating conditions.

Nap, doze and sleep modes for power savings.

Description

The PID7t-603e implementation of PowerPC603e (after named 603r) is a low-power implementa-

tion of reduced instruction set computer (RISC) microprocessors PowerPC™ family. The 603r is

pin-to-pin compatible with PowerPC 603E and 603P in Cerquad package. The 603r implements

32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of

32 and 64 bits.

The 603r is a low-power design and provides four software controllable power-saving modes.

The 603r is a superscalar processor capable of issuing and retiring as many as three instructions

per clock. Instructions can execute out of order for increased performance ; however, the 603r

makes completion appear sequential. The 603r integrates five execution units and is able to exe-

cute five instructions in parallel.

The 603r provides independent on-chip, 16-Kbyte, four-way set-associative, physically

addressed caches for instructions and data and on-chip instruction and data memory manage-

ment units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction

translation lookaside buffers that provide support for demand-paged virtual memory address

translation and variable-sized block translation.

The 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603r interface pro-

tocol allows multiple masters to complete for system resources through a central external arbiter.

The 603r supports single-beat and burst data transfers for memory accesses, and supports

memory-mapped I/O.

The 603r uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface

compatibility with TTL devices.

The 603r integrates in system testability and debugging features through JTAG boundary-scan

capability.

TSPC603r

in CERQUAD and

MQUAD Packages

PowerPC 603e

RISC

MICROPROCESSOR

Family PID7t-603e

Specification

Target Specification

Screening / Quality /Packaging

This product is manufactured in full

compliance with:

MIL-STD-883 class Q (TBC) or

According to TCS standards

Full military temperature range

= -55°C, T

= +125°C)

Industrial

temperature range

= -40°C, T

= +110°C)

Commercial temperature range

= 0°C, T

= +70°C)

Internal // I/O Power Supply

2.5

5 % // 3.3 V

5 %

240 pin Cerquad or 240 pin

MQUAD packages

MQUAD 240

CERQUAD 240

A suffix

CERQUAD 240

Ceramic Leaded Chip Carrier

Cavity up

Y suffix

MQUAD 240

Metal Quad Flat Pack

Cavity up

August 2000

1/40

1. INTRODUCTION

The 603r is a low-power implementation of the PowerPC microprocessor family of reduced instruction set commuter (RISC) micropro-

cessors. The 603r implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data

types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architec-

ture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.

The 603r provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in

nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management

mode that causes the functional units in the 603r to automatically enter a low-power mode when the functional units are idle without

affecting operational performance, software execution, or any external hardware.

The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute

out of order for increased performance ; however, the 603r makes completion appear sequential.

The 603 e integrates five execution units - an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store

unit (LSU) and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with

rapid execution times yield high efficiency and throughput for 603r-based systems. Most integer instructions execute in one clock

cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.

The 603r provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed caches for instructions and data

and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data

and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address

translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The

603r also supports block address translation through the use of two independent instruction and data block address translation (IBAT

and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during

block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT

translation takes priority.

The 603r has a selectable 32 - or 64-bit - data bus and a 32-bit address bus. The 603r interface protocol allows multiple masters to

compete for system resources through a central external arbiter. The 603r provides a three-state coherency protocol that supports the

exclusive, modified, and invalid cache states. This protocol as a compatible subset of the MESI (modified/exclusive/shared/invalid)

four-state protocol and operates coherently in systems that contain four-state caches. The 603r supports single-beat and burst data

transfers for memory accesses, and supports memory-mapped I/O.

The 603r uses an advanced, 0.29

5 metal layer CMOS process technology and maintains full interface compatibility with TTL

devices.

4/40

TSPC603r

in CERQUAD and MQUAD Packages

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