Preliminary
GS815218/36/72B-225/200/180/166/150/133
119- and 209-Pin BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive
• On-chip parity encoding and error detection
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 209-bump BGA package
1M x 18, 512K x 36, 256K x 72
16Mb S/DCD Sync Burst SRAMs
Flow Through/Pipeline Reads
200 MHz–133MHz
3.3 V V
DD
2.5 V or 3.3 V I/O
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS815218/36/72B is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
-225 -200 -180 -166
7.0 7.5 8.0 8.5
Flow
t
KQ
8.5 10.0 10.0 10.0
Through
tCycle
2-1-1-1 Curr (x18) 205 185 185 185
Curr (x36) 240 210 210 210
Curr (x72) 325 285 285 285
2.5 3.0 3.2 3.5
Pipeline
t
KQ
4.4 5.0 5.5 6.0
3-1-1-1
tCycle
Curr (x18) 350 315 290 270
Curr (x36) 410 370 340 315
Curr (x72) 570 515 470 435
-150
10.0
10.0
185
210
285
3.8
6.7
250
290
400
-133
11.0
15.0
140
160
205
4.0
7.5
230
260
360
Unit
ns
ns
mA
mA
mA
ns
ns
mA
mA
mA
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Functional Description
Applications
The GS815218/36/72B is a 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
ByteSafe™ Parity Functions
The GS815218/36/72B features ByteSafe data security functions.
See the detailed discussion following.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS815218/36/72B operates on a 3.3 V power supply. All
input are 3.3 V- and 2.5 V-compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V- and 2.5 V-compatible.
Rev: 1.01 11/2000
1/38
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary
GS815218/36/72B-225/200/180/166/150/133
GS815272 Pad Out
209 Bump BGA—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Rev 9.7
DQG5
DQG6
DQG7
DQG8
DQG9
DQC4
DQC3
DQC2
DQC1
NC
DQH1
DQH2
DQH3
DQH4
DQD9
DQD8
DQD7
DQD6
DQD5
2
DQG1
DQG2
DQG3
DQG4
DQC9
DQC8
DQC7
DQC6
DQC5
NC
DQH5
DQH6
DQH7
DQH8
DQH9
DQD4
DQD3
DQD2
DQD1
3
A15
BC
BH
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A9
TMS
4
E2
BG
BD
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A14
A8
TDI
5
ADSP
NC
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A13
A7
A3
6
ADSC
BW
E1
G
V
DD
ZQ
MCH
MCL
MCL
MCL
FT
MCL
SCD
ZZ
V
DD
LBO
A12
A1
A0
7
ADV
A16
NC
GW
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
PE
A11
A6
A2
8
E3
BB
BE
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A10
A5
TDO
9
A17
BF
BA
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
DP
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A4
TCK
10
DQB1
DQB2
DQB3
DQB4
DQF9
DQF8
DQF7
DQF6
DQF5
NC
DQA5
DQA6
DQA7
DQA8
DQA9
DQE4
DQE3
DQE2
DQE1
11
DQB5
DQB6
DQB7
DQB8
DQB9
DQF4
DQF3
DQF2
DQF1
QE
DQA1
DQA2
DQA3
DQA4
DQE9
DQE8
DQE7
DQE6
DQE5
11 x 19 Bump BGA—14 x 22 mm
2
Body—1 mm Bump Pitch
Rev: 1.01 11/2000
2/38
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
GS815272 BGA Pin Description
Pin Location
W6, V6
W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6,
U5, U4, A3, B7, A9
L11, M11, N11, P11, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, VV2, U2, T2, W1, V1, U1, T1, R1
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2
C9, B8, B3, C4, C8, B9, B4, C3
B5, C5, C7, D4, D5, D8, K1, K2, K4, K8, K10,
T4, T5, T8, U3, U9
K3
D7
C6, A8
A4
D6
A7
A5, A6
P6
L6
T6
N6
G6
H6, J6, K6, M6
T7
Symbol
A
0
, A
1
An
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D9
DQ
E1
–DQ
E9
DQ
F1
–DQ
F9
DQ
G1
–DQ
G9
DQ
H1
–DQ
H9
B
A
, B
B
, B
C
,B
D,
B
E
, B
F
, B
G
,B
H
NC
CK
GW
E
1,
E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
SCD
MCH
MCL
PE
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
I/O
Data Input and Output pins (x36 Version)
I
-
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D,
DQ
E
,
DQ
F
, DQ
G
, DQ
H
I/Os; active low
No Connect
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
Must Connect Low
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36
Mode)
I
Rev: 1.01 11/2000
3/38
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
GS815272 BGA Pin Description
Pin Location
K9
K11
F6
W2
W4
W8
W9
E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,
R6, R7
C3, C9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,
H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,
P4, P5, P7, P8, P9, T3, T9
E3, E4, E8, E0, G3, G4, G8, G9, J3, J4, J8, J9,
L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9
Symbol
DP
QE
ZQ
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
Type
I
O
I
I
I
O
I
I
I
I
Description
Data Parity Mode Input; 1 = Even, 0 = Odd
Parity Error Out; Open Drain Output
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.01 11/2000
4/38
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
GS815236 Pad Out
119 Bump BGA
—
Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
C4
DQ
C3
V
DDQ
DQ
C2
DQ
C1
V
DDQ
DQ
D1
DQ
D2
V
DDQ
DQ
D3
DQ
D4
NC
NC
V
DDQ
2
A
6
A
18
A
5
DQ
C9
DQ
C8
DQ
C7
DQ
C6
DQ
C5
V
DD
DQ
D5
DQ
D6
DQ
D7
DQ
D8
DQ
D9
A
2
NC
TMS
3
A
7
A
4
A
3
V
SS
V
SS
V
SS
B
C
V
SS
DP
V
SS
B
D
V
SS
V
SS
V
SS
LBO
A
10
TDI
4
ADSP
ADSC
V
DD
ZQ
E
1
G
ADV
GW
V
DD
CK
SCD
BW
A
1
A
0
V
DD
A
11
TCK
5
A
8
A
15
A
14
V
SS
V
SS
V
SS
B
B
V
SS
QE
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
12
TDO
6
A
9
A
17
A
16
DQ
B9
DQ
B8
DQ
B7
DQ
B6
DQ
B5
V
DD
DQ
A5
DQ
A6
DQ
A7
DQ
A8
DQ
A9
A
13
NC
NC
7
V
DDQ
NC
NC
DQ
B4
DQ
B3
V
DDQ
DQ
B2
DQ
B1
V
DDQ
DQ
A1
DQ
A2
V
DDQ
DQ
A3
DQ
A4
PE
ZZ
V
DDQ
Rev: 1.01 11/2000
5/38
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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