CSPU877ANLG8 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> CSPU877ANLG8

CSPU877ANLG8: DescriptionVFQFPN-40, Reel; Categorylogic logic; File Size264KB，14 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

Download Datasheet Parametric Compare View All

CSPU877ANLG8 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	CSPU877ANLG8	-	-	View	Buy Now

CSPU877ANLG8 Overview

VFQFPN-40, Reel

CSPU877ANLG8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN
package instruction	VQCCN, LCC40,.24SQ,20
Contacts	40
Manufacturer packaging code	NLG40P1
Reach Compliance Code	compliant
ECCN code	EAR99
series	877
Input adjustment	DIFFERENTIAL
JESD-30 code	S-PQCC-N40
JESD-609 code	e3
length	6 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.009 A
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	40
Actual output times	10
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	VQCCN
Encapsulate equivalent code	LCC40,.24SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.04 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	6 mm
minfmax	340 MHz

Preview

Download Datasheet

View All

IDTCSPU877A

1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

COMMERCIAL TEMPERATURE RANGE

1.8V PHASE LOCKED LOOP

DIFFERENTIAL 1:10 SDRAM

CLOCK DRIVER

FEATURES:

DESCRIPTION:

IDTCSPU877A

• 1 to 10 differential clock distribution

• Optimized for clock distribution in DDR2 (Double Data Rate)

SDRAM applications

• Operating frequency: 125MHz to 340MHz

• Very low skew:

≤

40ps

• Very low jitter:

≤

40ps

• 1.8V AV

and 1.8V V

DDQ

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

• Available in 52-Ball VFBGA and 40-pin VFQFPN packages

APPLICATIONS:

• Meets or exceeds JEDEC standard 82.8 for registered DDR2

clock driver

• Along with SSTU32864/65/66, DDR2 register, provides complete

solution for DDR2 DIMMs

The CSPU877A is a PLL based clock driver that acts as a zero delay buffer

to distribute one differential clock input pair(CLK,

CLK

) to 10 differential

output pairs (Y

[0:9]

, Y

[0:9]

) and one differential pair of feedback clock output

(FBOUT,

FBOUT).

External feedback pins (FBIN,

FBIN)

for synchronization

of the outputs to the input reference is provided. OE, OS, and A

VDD

control the

power-down and test mode logic. When A

VDD

is grounded, the PLL is turned

off and bypassed for test mode purposes. When the differential clock inputs

(CLK,

CLK)

are both at logic low, this device will enter a low power-down mode.

In this mode, the receivers are disabled, the PLL is turned off, and the output

clock drivers are disabled, resulting in a current consumption device of less than

500μA.

The CSPU877A requires no external components and has been optimised

for very low phase error, skew, and jitter, while maintaining frequency and duty

cycle over the operating voltage and temperature range. The CSPU877A,

designed for use in both module assemblies and system motherboard based

solutions, provides an optimum high-performance clock source.

The CSPU877A is available in Commercial Temperature Range (0°C to

+70°C). See Ordering Information for details.

FUNCTIONAL BLOCK DIAGRAM

LD or OE

POWER

DOWN

AND

LD, OS, or OE

TEST

MODE

PLL BYPASS

LOGIC

CLK

10KΩ - 100KΩ

FBIN

PLL

NOTE:

The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and

CLK.

FBOUT

COMMERCIAL TEMPERATURE RANGE

2006

Integrated Device Technology, Inc.

FBOUT

OCTOBER 2006

DSC-6495/8

CSPU877ANLG8 Related Products

	CSPU877ANLG8	CSPU877ABVG	CSPU877ANLG
Description	VFQFPN-40, Reel	CABGA-52, Tray	VFQFPN-40, Tray
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to
Parts packaging code	VFQFPN	CABGA	VFQFPN
package instruction	VQCCN, LCC40,.24SQ,20	TFBGA, BGA52,6X10,25	VQCCN, LCC40,.24SQ,20
Contacts	40	52	40
Manufacturer packaging code	NLG40P1	BVG52	NLG40P1
Reach Compliance Code	compliant	unknown	compliant
ECCN code	EAR99	EAR99	EAR99
series	877	877	877
Input adjustment	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL
JESD-30 code	S-PQCC-N40	R-PBGA-B52	S-PQCC-N40
JESD-609 code	e3	e1	e3
length	6 mm	7 mm	6 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.009 A	0.009 A	0.009 A
Humidity sensitivity level	3	3	3
Number of functions	1	1	1
Number of terminals	40	52	40
Actual output times	10	10	10
Maximum operating temperature	70 °C	70 °C	70 °C
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VQCCN	TFBGA	VQCCN
Encapsulate equivalent code	LCC40,.24SQ,20	BGA52,6X10,25	LCC40,.24SQ,20
Package shape	SQUARE	RECTANGULAR	SQUARE
Package form	CHIP CARRIER, VERY THIN PROFILE	GRID ARRAY, THIN PROFILE, FINE PITCH	CHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260	260
power supply	1.8 V	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.04 ns	0.04 ns	0.04 ns
Maximum seat height	1 mm	1.05 mm	1 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed	Tin/Silver/Copper (Sn/Ag/Cu)	Matte Tin (Sn) - annealed
Terminal form	NO LEAD	BALL	NO LEAD
Terminal pitch	0.5 mm	0.65 mm	0.5 mm
Terminal location	QUAD	BOTTOM	QUAD
Maximum time at peak reflow temperature	30	30	30
width	6 mm	4.5 mm	6 mm
minfmax	340 MHz	340 MHz	340 MHz
Maker	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)

Recommended Resources

Thyristor and 555 time base integrated circuit interface circuit

Full digital triac circuit diagram

Simple power supply fixed voltage circuit diagram

Use the TV remote control to turn off the power to electrical appliances

Railway-specific 150MHz ultra-short wave interference direction finder circuit

Tracking integrated regulated power supply composed of two integrated voltage regulators

liunx configures static IP and changes ens33 network card to eth0: 【】Modify the network card and change ens33 to eth01. Edit the gurb configuration filevim /etc/sysconfig/grubModify the GRUB_CMDLINE_LINUX variable and add two parametersGRUB_CMDLINE_LINUX="crashkernel...; 灞波儿奔 Microcontroller MCU

"Practice Together in 2021" + An Ordinary Year: Overall, 2020 was an average year. Although I was busy this year, I felt like I accomplished nothing and was quite confused. The project I am working on has not yet been put into mass production due t...; tomjianchun.xu Talking

Giant Digital Caliper Clock: Digital caliper style clockhttps://boingboing.net/2022/01/29/building-a-wall-size-digital-calipers-clock.html...; dcexpert MicroPython Open Source section

FPGA learning and design considerations V.1.pdf: FPGA learning and design considerations V.1.pdf...; zxopenljx EE_FPGA Learning Park

After the imx6 fuse is modified, it cannot start and the debug serial port has no response. Is there any way to save it?: As the title!!!...; 新世纪好青年 ARM Technology

TIOBE Index June 2022: C++ is about to surpass Java: Java seems to be on the losing side. In April 2020, Java was still the number one in the TIOBE index. In the same month, Java had to give up the number one spot to C. Later, in 2021, Python was unstop...; dcexpert MicroPython Open Source section

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components