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CSPU877ANLG

Description
VFQFPN-40, Tray
Categorylogic    logic   
File Size264KB,14 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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CSPU877ANLG Overview

VFQFPN-40, Tray

CSPU877ANLG Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeVFQFPN
package instructionVQCCN, LCC40,.24SQ,20
Contacts40
Manufacturer packaging codeNLG40P1
Reach Compliance Codecompliant
ECCN codeEAR99
series877
Input adjustmentDIFFERENTIAL
JESD-30 codeS-PQCC-N40
JESD-609 codee3
length6 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
MaximumI(ol)0.009 A
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals40
Actual output times10
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeVQCCN
Encapsulate equivalent codeLCC40,.24SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply1.8 V
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.04 ns
Maximum seat height1 mm
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width6 mm
minfmax340 MHz
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
FEATURES:
DESCRIPTION:
IDTCSPU877A
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 (Double Data Rate)
SDRAM applications
• Operating frequency: 125MHz to 340MHz
• Very low skew:
40ps
• Very low jitter:
40ps
• 1.8V AV
DD
and 1.8V V
DDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 52-Ball VFBGA and 40-pin VFQFPN packages
APPLICATIONS:
• Meets or exceeds JEDEC standard 82.8 for registered DDR2
clock driver
• Along with SSTU32864/65/66, DDR2 register, provides complete
solution for DDR2 DIMMs
The CSPU877A is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK,
CLK
) to 10 differential
output pairs (Y
[0:9]
, Y
[0:9]
) and one differential pair of feedback clock output
(FBOUT,
FBOUT).
External feedback pins (FBIN,
FBIN)
for synchronization
of the outputs to the input reference is provided. OE, OS, and A
VDD
control the
power-down and test mode logic. When A
VDD
is grounded, the PLL is turned
off and bypassed for test mode purposes. When the differential clock inputs
(CLK,
CLK)
are both at logic low, this device will enter a low power-down mode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clock drivers are disabled, resulting in a current consumption device of less than
500μA.
The CSPU877A requires no external components and has been optimised
for very low phase error, skew, and jitter, while maintaining frequency and duty
cycle over the operating voltage and temperature range. The CSPU877A,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPU877A is available in Commercial Temperature Range (0°C to
+70°C). See Ordering Information for details.
FUNCTIONAL BLOCK DIAGRAM
OE
OS
AV
DD
LD or OE
POWER
DOWN
AND
LD, OS, or OE
TEST
MODE
PLL BYPASS
LOGIC
LD
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
CLK
CLK
10KΩ - 100KΩ
FBIN
FBIN
PLL
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and
CLK.
Y9
FBOUT
COMMERCIAL TEMPERATURE RANGE
1
c
2006
Integrated Device Technology, Inc.
FBOUT
OCTOBER 2006
DSC-6495/8

CSPU877ANLG Related Products

CSPU877ANLG CSPU877ABVG CSPU877ANLG8
Description VFQFPN-40, Tray CABGA-52, Tray VFQFPN-40, Reel
Brand Name Integrated Device Technology Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to
Parts packaging code VFQFPN CABGA VFQFPN
package instruction VQCCN, LCC40,.24SQ,20 TFBGA, BGA52,6X10,25 VQCCN, LCC40,.24SQ,20
Contacts 40 52 40
Manufacturer packaging code NLG40P1 BVG52 NLG40P1
Reach Compliance Code compliant unknown compliant
ECCN code EAR99 EAR99 EAR99
series 877 877 877
Input adjustment DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL
JESD-30 code S-PQCC-N40 R-PBGA-B52 S-PQCC-N40
JESD-609 code e3 e1 e3
length 6 mm 7 mm 6 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
MaximumI(ol) 0.009 A 0.009 A 0.009 A
Humidity sensitivity level 3 3 3
Number of functions 1 1 1
Number of terminals 40 52 40
Actual output times 10 10 10
Maximum operating temperature 70 °C 70 °C 70 °C
Output characteristics 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code VQCCN TFBGA VQCCN
Encapsulate equivalent code LCC40,.24SQ,20 BGA52,6X10,25 LCC40,.24SQ,20
Package shape SQUARE RECTANGULAR SQUARE
Package form CHIP CARRIER, VERY THIN PROFILE GRID ARRAY, THIN PROFILE, FINE PITCH CHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260 260
power supply 1.8 V 1.8 V 1.8 V
Certification status Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.04 ns 0.04 ns 0.04 ns
Maximum seat height 1 mm 1.05 mm 1 mm
Maximum supply voltage (Vsup) 1.9 V 1.9 V 1.9 V
Minimum supply voltage (Vsup) 1.7 V 1.7 V 1.7 V
Nominal supply voltage (Vsup) 1.8 V 1.8 V 1.8 V
surface mount YES YES YES
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) - annealed Tin/Silver/Copper (Sn/Ag/Cu) Matte Tin (Sn) - annealed
Terminal form NO LEAD BALL NO LEAD
Terminal pitch 0.5 mm 0.65 mm 0.5 mm
Terminal location QUAD BOTTOM QUAD
Maximum time at peak reflow temperature 30 30 30
width 6 mm 4.5 mm 6 mm
minfmax 340 MHz 340 MHz 340 MHz
Maker IDT (Integrated Device Technology) - IDT (Integrated Device Technology)
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