M24L416256SA datasheet, PDF - EEWORLD Datasheet

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M24L416256SA: Description4-Mbit (256K x 16) Pseudo Static RAM; File Size316KB，14 Pages; ManufacturerESMT; Websitehttp://www.esmt.com.tw/; Elite Semiconductor Memory Technology Inc. (ESMT) is a professional IC design company founded by Dr. Hu Zhao in June 1998. Its headquarters is located in Hsinchu Science Park, Taiwan. The company's main business includes research, development, manufacturing, sales and related technical services of IC products. It was listed on the Taiwan Stock Exchange in March 2002.

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M24L416256SA Overview

4-Mbit (256K x 16) Pseudo Static RAM

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ESMT

PSRAM

Features

• Wide voltage range: 2.7V–3.6V

• Access time: 55 ns, 60 ns and 70 ns

• Ultra-low active power

— Typical active current: 1 mA @ f = 1 MHz

— Typical active current: 8 mA @ f = fmax (70-ns speed)

• Ultra low standby power

• Automatic power-down when deselected

• CMOS for optimum speed/power

M24L416256SA

4-Mbit (256K x 16) Pseudo Static RAM

The input/output pins (I/O0through I/O

) are placed in a

high-impedance state when : deselected ( CE HIGH), outputs

are disabled (

HIGH), both Byte High Enable and Byte

Low Enable are disabled (

BHE

BLE

HIGH), or during a write

operation ( CE LOW and

LOW).

Writing to the device is accomplished by taking Chip

Enable( CE LOW) and Write Enable (

) input LOW. If Byte

Low Enable (

BLE

) is LOW, then data from I/O pins (I/O

through I/O

) is written into the location specified on the

address pins(A

through A

). If Byte High Enable (

BHE

) is

LOW, then data from I/O pins (I/O

through I/O

) is written into

the location specified on the address pins (A

through A

Reading from the device is accomplished by taking Chip

Enable ( CE LOW) and Output Enable ( OE ) LOW while

forcing the Write Enable (

) HIGH. If Byte Low Enable

(

BLE

) is LOW, then data from the memory location specified

by the address pins will appear on I/O

to I/O

. If Byte High

Enable(

BHE

) is LOW, then data from memory will appear on

I/O

toI/O

. Refer to the truth table for a complete description

of read and write modes.

Functional Description

The M24L416256SA is a high-performance CMOS Pseudo

static RAM organized as 256K words by 16 bits that supports

an asynchronous memory interface. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for portable applications such as cellular

telephones. The device can be put into standby mode when

deselected ( CE HIGH or both

BHE

and

BLE

are HIGH).

Logic Block Diagram

Elite Semiconductor Memory Technology Inc.

Publication Date: Jul. 2008

Revision: 1.4

1/14

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