Ordering number : ENA1463A
CMOS IC
LE24LA322CS
Overview
Two Wire Serial Interface
EEPROM (32k EEPROM)
The LE24LA322CS is a 2-wire serial interface EEPROM. It realizes high speed and a high level reliability by
incorporating SANYO’s high performance CMOS EEPROM technology. This device is compatible with I
2
C memory
protocol, therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory.
Functions
•
Capacity: 32k bits (4k
×
8 bits)
•
Single supply voltage: 1.7V to 3.6V
•
Interface: Two wire serial interface (I
2
C Bus*)
•
slave addresses: S2=0, S1=1, S0=0
•
Operating clock frequency: 400kHz
•
Low power consumption
: Standby: 2μA (max)
: Active (Read): 0.5mA (max)
•
Automatic page write mode: 32 Bytes
•
Read mode: Sequential read and random read
•
Erase/Write cycles: 10
5
cycles
•
Data Retention: 10 years
•
High reliability: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325)
Noise filters connected to SCL and SDA pins
Incorporates a feature to prohibit write operations under low voltage conditions.
•
Package : LE24LA322CS-TL2 : WLP6
* I
2
C Bus is a trademark of Philips Corporation.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer
'
s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
'
s products or
equipment.
61009 SY / 42809 SY 20090401-S00010 No.A1463-1/11
LE24LA322CS
DC Electrical Characteristics
Parameter
Supply current at reading
Supply current at writing
Standby current
Input leakage current
Output leakage current (SDA)
Input low voltage
Input low voltage (CMOS)
Input high voltage
Input high voltage (CMOS)
Output low voltage
Symbol
ICC1
ICC2
ISB
ILI
ILO
VIL
VILC
VIH
VIHC
VOL
IOL=0.7mA, VDD=1.7V
IOL=2.0mA, VDD=2.5V
VDD*0.8
VDD-0.2
0.2
0.4
f=400kHz
f=400kHz
VIN=VDD or GND
VIN=GND to VDD
VOUT=GND to VDD
-2.0
-2.0
Conditions
min
VDD=1.7V to 3.6V
typ
max
0.5
3
2
+2.0
+2.0
VDD*0.2
0.2
mA
mA
μA
μA
μA
V
V
V
V
V
V
unit
Capacitance/Ta=25°C,
f=1MHz
Parameter
In/Output pin capacitance
Input pin capacitance
Symbol
CI/O
CI
VI/O=0V (SDA)
VIN=0V (other than SDA)
Conditions
max
10
10
unit
pF
pF
Note: This parameter is sampled and not 100% tested.
AC Electric Characteristics
Input pulse level
Input pulse rise / fall time
Output detection voltage
Output load
0.1×VDD to 0.9×VDD
20ns
0.5×VDD
50pF+Pull up resistor 3.0kΩ
VDD
R=3.0kΩ
SDA
C=50pF
Output Load Circuit
Parameter
Slave mode SCL clock frequency
SCL clock low time
SCL clock high time
SDA output delay time
SDA data output hold time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
SCL SDA rise time
SCL SDA fall time
Bus release time
Noise suppression time
Write cycle time
Symbol
min
fSCLS
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tSP
tWC
1200
0
1200
600
100
100
600
600
100
0
600
VDD=1.7V to 3.6V
typ
max
400
unit
kHz
ns
ns
900
ns
ns
ns
ns
ns
ns
ns
300
300
ns
ns
ns
100
10
ns
ms
No.A1463-3/11
LE24LA322CS
Bus Timing
tF
tHIGH
tLOW
tR
tSP
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
tSP
tAA
SDA/OUT
tDH
tBUF
SCL
tSU.STA
SDA/IN
Write Timing
tWC
SCL
SDA
D0
Write Data
Acknowledge
Stop
condition
Start
condition
Pin Functions
SCL (serial clock input) pin
The SCL pin is a serial clock input pin that processes signals at the rising and falling edges of SCL clock signals.
SDA (serial data input/output) pin
The SDA pin is used to transfer serial data to the input/output, and it consists of a signal input pin and n-channel
transistor open drain output pin.
Like the SCL pin, the SDA pin must be pulled up by a resistor to the VDD level and wired-ORed with an open drain
(or open collector) output device for use.
WP (write protect) pin
When the WP pin is high, write protection is enabled, and writing into the 32k bit memory areas is prohibited. When
the pin is low, writing is possible to all memory areas. Read operations can be performed regardless of the WP pin
status.
No.A1463-4/11
LE24LA322CS
Functional Description
1 Start condition
When the SCL line is at the high level, the start condition is established by changing the SDA line from high to low.
The operation of the EEPROM as a slave starts in the start condition.
2 Stop condition
When the SCL line is at the high level, the stop condition is established by changing the SDA line from low to high.
When the device is set up for the read sequence, the read operation is suspended when the stop condition is received,
and the device is set to standby mode. When it is set up for the write sequence, the capture of the write data is ended
when the stop condition is received, and the EEPROM internal write operation is started.
tSU.STA
tHD.STA
tSU.STO
SCL
SDA
Start
condition
Stop
condition
3 Data transfer
Data is transferred by changing the SDA line while the SCL line is low. When the SDA line is changed while the SCL
line is high, the resulting condition will be recognized as the start or stop condition.
tSU.DAT
tHD.DAT
SCL
SDA
4 Acknowledge
During data transfer, 8-bits are transferred in succession, and then in the ninth clock cycle period the device on the
system bus receiving the data sets the SDA line to low, and sends the acknowledge signal indicating that the data has
been received. The acknowledge signal is not sent during an EEPROM internal write operation.
SCL
(EEPROM input)
1
8
9
SDA
(Master output)
Acknowledge
bit output
Start
condition
tAA
tDH
SDA
(EEPROM output)
No.A1463-5/11
Microcontroller MCU
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