HY27SS16121M-FIB datasheet, PDF

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HY27SS16121M-FIB: DescriptionFlash, 32MX16, 12000ns, PBGA63, 8.50 X 15 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, FBGA-63; Categorystorage storage; File Size730KB，43 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY27SS16121M-FIB Overview

Flash, 32MX16, 12000ns, PBGA63, 8.50 X 15 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, FBGA-63

HY27SS16121M-FIB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA,
Contacts	63
Reach Compliance Code	unknown
ECCN code	3A991.B.1.A
Maximum access time	12000 ns
JESD-30 code	R-PBGA-B63
length	15 mm
memory density	536870912 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of terminals	63
word count	33554432 words
character code	32000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programming voltage	1.8 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8.5 mm
Base Number Matches	1

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HY27SS(08/16)121M Series

HY27US(08/16)121M Series

512Mbit (64Mx8bit / 32Mx16bit) NAND Flash

Document Title

512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory

Revision History

No.

0.0

0.1

0.2

0.3

Initial Draft

Renewal Product Group

Make a decision of PKG information

Append 1.8V Operation Product to Data sheet

1) Add Errata

tWC

Specification

0.4

Relaxed value

tWH

tWP

tRC

tREH

tRP

tREA@ID Read

Mar.28.2004

Preliminary

History

Draft Date

Sep.17.2003

Oct.07.2003

Nov.08.2003

Dec.01.2003

Remark

Preliminary

2) Modify the description of Device Operations

- /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled

(Enabled) (Page22)

3) Add the description of System Interface Using CE don’t care

(Page37)

1) Delete Errata

2) Change Characteristics (3V Product)

0.5

tCRY

Before

After

60 + tr

70 + tr

tREA@ID Read

Jun. 01. 2004

Preliminary

3) Delete Cache Program

0.6

1) Change TSOP1, WSOP1, FBGA package dimension

2) Edit TSOP1, WSOP1 package figures

3) Change FBGA package figure

Oct. 20. 2004

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 0.6 / Oct. 2004

HY27SS(08/16)121M Series

HY27US(08/16)121M Series

512Mbit (64Mx8bit / 32Mx16bit) NAND Flash

DESCRIPTION

The HYNIX HY27(U/S)SXX121M series is a family of non-volatile Flash memories that use NAND cell technology. The

devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words

(256 + 8 spare) depending on whether the device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 or x16 Input/ Output bus.

This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.

Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is

strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hard-

ware protection against program and erase operations.

The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (PER)

Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to

be connected to a single pull-up resistor.

A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation

fails, the data can be programmed in another page without having to resend the data to be programmed.

The devices are available in the following packages:

48-TSOP1

(12 x 20 x 1.2 mm)

- 48-WSOP1

(12 x 17 x 0.7 mm)

- 63-FBGA

(8.5 x 15 x 1.2 mm, 6 x 8 ball array, 0.8mm pitch)

Three options are available for the NAND Flash family:

- Automatic Page 0 Read after Power-up, which allows the microcontroller to directly download the boot code from

page 0.

- Chip Enable Dont Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions

during the latency time do not stop the read operation.

- A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA

(Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your near-

est HYNIX Sales office.

Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to

'1'.

Rev 0.6 / Oct. 2004

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