HD74ALVC162834AT-EL datasheet, PDF

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HD74ALVC162834AT-EL: DescriptionALVC/VCX/A SERIES, 18-BIT DRIVER, INVERTED OUTPUT, PDSO56, TSSOP-56; Categorylogic logic; File Size88KB，17 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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HD74ALVC162834AT-EL Overview

ALVC/VCX/A SERIES, 18-BIT DRIVER, INVERTED OUTPUT, PDSO56, TSSOP-56

HD74ALVC162834AT-EL Parametric

Parameter Name	Attribute value
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	56
Reach Compliance Code	unknow
series	ALVC/VCX/A
JESD-30 code	R-PDSO-G56
length	14 mm
Logic integrated circuit type	BUS DRIVER
Number of digits	18
Number of functions	1
Number of ports	2
Number of terminals	56
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	INVERTED
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	6.3 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
width	6.1 mm
Base Number Matches	1

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HD74ALVC162834A

18-bit Universal Bus Driver with 3-state Outputs

and Inverted Latch Enable

ADE-205-293B (Z)

Rev. 2

Oct. 2001

Description

The HD74ALVC162834A is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V

operation.

Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode

when the latch enable (LE) is low. When

is low, the A data is latched if the clock (CLK) input is held

at a high or low logic level. If the

is high, the A data is stored in the latch/flip flop on the low to high

transition of CLK. When

is high, the outputs are in the high impedance state.

To ensure the high impedance state during power up or power down,

should be tied to V

through a

pullup registor; the minimum value of the registor is determined by the current sinking capability of the

driver.

All outputs, which are designed to sink up to 12 mA, include series dumping resistors to reduce overshoot

and undershoot.

Features

•

Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”

•

= 2.3 V to 3.6 V

•

Typical V

ground bounce < 0.8 V (@V

= 3.3 V, Ta = 25°C)

•

Typical V

undershoot > 2.0 V (@V

= 3.3 V, Ta = 25°C)

•

High output current ±12 mA (@V

= 3.0 V)

•

All outputs have series dumping resistors, so no external resistors are required

•

(CLK to Y) = 3.5 ns (Max) (@V

= 3.3±0.3 V, C

= 50 pF, Ta = 0 to 85°C)

•

(CLK to Y) = 2.5 ns (Max) (@V

= 3.3±0.3 V, C

= 30 pF, Ta = 0 to 85°C)

•

Package type

TSSOP-56pin

TVSOP-56pin

Package code

TTP-56DAV

TTP-56DBV

Package suffix

Taping code

EL(1000pcs / Reel)

HD74ALVC162834AT-EL Related Products

	HD74ALVC162834AT-EL	HD74ALVC162834AT	HD74ALVC162834AN	HD74ALVC162834AN-EL
Description	ALVC/VCX/A SERIES, 18-BIT DRIVER, INVERTED OUTPUT, PDSO56, TSSOP-56	ALVC/VCX/A SERIES, 18-BIT DRIVER, INVERTED OUTPUT, PDSO56, TSSOP-56	ALVC/VCX/A SERIES, 18-BIT DRIVER, INVERTED OUTPUT, PDSO56, TVSOP-56	ALVC/VCX/A SERIES, 18-BIT DRIVER, INVERTED OUTPUT, PDSO56, TVSOP-56
Parts packaging code	TSSOP	TSSOP	SSOP	SSOP
package instruction	TSSOP,	TSSOP,	TSSOP,	TSSOP,
Contacts	56	56	56	56
Reach Compliance Code	unknow	compliant	compliant	compliant
series	ALVC/VCX/A	ALVC/VCX/A	ALVC/VCX/A	ALVC/VCX/A
JESD-30 code	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56
length	14 mm	14 mm	11.3 mm	11.3 mm
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
Number of digits	18	18	18	18
Number of functions	1	1	1	1
Number of ports	2	2	2	2
Number of terminals	56	56	56	56
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	INVERTED	INVERTED	INVERTED	INVERTED
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	6.3 ns	6.3 ns	6.3 ns	6.3 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.4 mm	0.4 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	6.1 mm	6.1 mm	4.4 mm	4.4 mm
Maker	-	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation

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